HT46C23 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT46C23

A/D Type 8-Bit MCU

Holtek Semiconductor 

HT46R23/HT46C23

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic operations.

The ALU provides the following functions:

· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation but

also changes the status register.

Status Register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF), and watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

With the exception of the TO and PDF flags, bits in

the status register can be altered by instructions like

most other registers. Any data written into the status

register will not change the TO or PDF flag. In addi-

tion operations related to the status register may give

different results from those intended. The TO flag

can be affected only by system power-up, a WDT

time-out or executing the ²CLR WDT² or ²HALT² in-

struction. The PDF flag can be affected only by exe-

cuting the ²HALT² or ²CLR WDT² instruction or a

system power-up.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

Interrupt

The device provides an external interrupt, an internal

timer/event counter interrupt, the A/D converter interrupt

and the I2C Bus interrupts. The interrupt control register

0 (INTC0;0BH) and interrupt control register 1

(INTC1;1EH) contains the interrupt control bits to set the

enable or disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt requires servicing within the service routine, the

EMI bit and the corresponding bit of INTC0 and INTC1

may be set to allow interrupt nesting. If the stack is full,

the interrupt request will not be acknowledged, even if the

related interrupt is enabled, until the SP is decremented.

If immediate service is desired, the stack must be pre-

vented from becoming full.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

External interrupts are triggered by a high to low transi-

tion of INT and the related interrupt request flag (EIF; bit

4 of INTC0) will be set. When the interrupt is enabled,

the stack is not full and the external interrupt is active, a

subroutine call to location 04H will occur. The interrupt

request flag (EIF) and EMI bits will be cleared to disable

other interrupts.

Labels Bits

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not take

C

0 place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through

carry instruction.

AC

1

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z

2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV

3

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the high-

est-order bit, or vice versa; otherwise OV is cleared.

PDF

4

PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by exe-

cuting the ²HALT² instruction.

TO

5

TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set

by a WDT time-out.

¾

6, 7 Unused bit, read as ²0²

Status Register

Rev. 1.60

9

May 3, 2004

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