HT46R49E 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT46R49E Datasheet PDF : 73 Pages
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HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
Symbol
Parameter
tRES
External Reset Low Pulse Width
Test Conditions
VDD
Conditions
¾
¾
tSST
System Start-up Timer Period
¾ Wake-up from HALT
tLVR
Low Voltage Reset Time
¾
¾
tINT
Interrupt Pulse Width
¾
¾
tAD1
A/D Clock Period -
HT46R46E
¾
¾
tAD2
A/D Clock Period -
HT46R47E/HT46R48AE/HT46R49E
¾
¾
tADC1
A/D Conversion Time -
HT46R46E
¾
¾
tADC2
A/D Conversion Time -
HT46R47E/HT46R48AE/HT46R49E
¾
¾
tADCS1
A/D Sampling Time -
HT46R46E
¾
¾
tADCS2
A/D Sampling Time -
HT46R47E/HT46R48AE/HT46R49E
¾
¾
Min.
1
¾
0.25
1
0.5
1
¾
¾
¾
¾
Note: *tSYS=1/fSYS
Typ.
¾
1024
1
¾
¾
¾
64
76
32
32
Max.
¾
¾
2
¾
¾
¾
¾
¾
¾
¾
Unit
ms
*tSYS
ms
ms
ms
ms
tAD1
tAD2
tAD1
tAD2
EEPROM - A.C. Characteristics
Ta=25°C
Symbol
Parameter
fSK
tHIGH
tLOW
tr
tf
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time
SDA and SCL Fall Time
tHD:STA START Condition Hold Time
tSU:STA START Condition Setup Time
tHD:DAT
tSU:DAT
tSU:STO
tAA
Data Input Hold Time
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
tBUF
Bus Free Time
tSP
Input Filter Time Constant
(SDA and SCL Pins)
tWR
Write Cycle Time
Remark
Standard
Mode*
VCC=5V±10%
Unit
Min. Max. Min. Max.
¾
¾ 100 ¾ 400 kHz
¾
4000 ¾ 600 ¾
ns
¾
4700 ¾ 1200 ¾
ns
Note
¾ 1000 ¾ 300 ns
Note
¾ 300 ¾ 300 ns
After this period the
first clock pulse is
generated
4000 ¾ 600 ¾
ns
Only relevant for
repeated START
condition
4000 ¾ 600 ¾
ns
¾
0
¾
0
¾
ns
¾
200 ¾ 100 ¾
ns
¾
4000 ¾ 600 ¾
ns
¾
¾ 3500 ¾ 900 ns
Time in which the bus
must be free before a new 4700 ¾ 1200 ¾
ns
transmission can start
Noise suppression time ¾ 100 ¾
50
ns
¾
¾
5
¾
5
ms
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 5.5V
Rev. 1.20
7
August 15, 2007
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