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HT46R51A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R51A/HT46R52A

Table Location

Instruction

b10 b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

TABRDC [m]

P10 P9

P8

@7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m]

1

1

1

@7 @6 @5 @4 @3 @2 @1 @0

Table Location

Note:

b10~b0: Table location bits

P10~P8: Current program counter bits

@7~@0: Table pointer bits

For the Ht46R51A, since the program counter is 10 bits wide (b0~b9), the b10 column in the table are not appli-

cable

For the HT46R52A, since the program counter is 11 bits wide (b0~b10)

Stack Register - STACK

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 6 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At the state of a subroutine call or an interrupt acknowl-

edgment, the contents of the program counter are

pushed onto the stack. At the end of the subroutine or an

interrupt routine, signaled by a return instruction (RET or

RETI), the program counter is restored to its previous

value from the stack. After a chip reset, the SP will point

to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt is

serviced. This feature prevents stack overflow, allowing

the programmer to use the structure more easily. If the

stack is full and a ²CALL² is subsequently executed,

stack overflow occurs and the first entry will be lost (only

the most recent 6 return addresses are stored).

Data Memory - RAM

The data memory (RAM) is designed with 119´8 bits

(HT46R51A), 151´8 bits (HT46R52A) and is divided

into two functional groups, namely; special function reg-

isters (23´8 bits) and general purpose data memory

(96´8bit for HT46R51A, 128´8bit for HT46R52A) most

of which are readable/writable, although some are read

only. The unused space before 28H is reserved for fu-

ture expanded usage and reading these locations will

return the result ²00H². The general purpose data mem-

ory, addressed from 28H to 87H and 28H to A7H, is

used for data and control information under instruction

commands. All of the data memory areas can handle

arithmetic, logic, increment, decrement and rotate oper-

ations directly. Except for some dedicated bits, each bit

in the data memory can be set and reset by ²SET [m].i²

and ²CLR [m].i². They are also indirectly accessible

through memory pointer registers (MP0;01H or

MP1;03H).

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] ([02H]) will access the data memory

pointed to by MP0 (MP1). Reading location 00H (02H)

itself indirectly will return the result ²00H². Writing indi-

rectly results in no operation. A configuration option se-

lects whether the memory pointer registers, MP0 and

MP1, are 7-bit or 8-bit. If selected to be 7-bit registers,

then bit 7 of the Memory Pointers are not implemented.

However, it must be noted that when the Memory

Pointer for these devices is read, bit 7 will be read as a

high value. Note also that data memory addresses after

address 80H cannot be accessed by MP0 and MP1, if

MP0 and MP1 are selected as 7-bit registers.

Accumulator - ACC

The accumulator closely relates to ALU operations. It is

also mapped to location ²05H² of the data memory

which can operate with immediate data. The data move-

ment between two data memories has to pass through

the accumulator.

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic operations.

The ALU provides the following functions:

· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation

but also changes the status register.

Rev. 1.30

7

March 6, 2009

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