HT46R53A 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT46R53A Datasheet PDF : 43 Pages
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HT46R53A/HT46R54A
Bit No.
0
1
2
3
4
5
6~7
Label
C
AC
Z
OV
PDF
TO
¾
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
Unused bit, read as ²0²
Status (0AH) Register
Interrupts
The device provides an external interrupt, an internal
timer/event counter interrupt, and an A/D converter in-
terrupt. The interrupt control register (INTC;0BH) con-
tains the interrupt control bits to set the enable/disable
and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of the INTC) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location ²04H² will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal Timer/Event Counter interrupt is initialized
by setting the Timer/Event Counter interrupt request flag
(TF; bit 5 of the INTC), which is normally caused by a
timer overflow. After the interrupt is enabled, and the
stack is not full, and the TF bit is set, a subroutine call to
location ²08H² occurs. The related interrupt request flag
(TF) is reset, and the EMI bit is cleared to disable further
maskable interrupts.
Bit No.
0
1
2
3
4
5
6
7
Label
EMI
EEI
ETI
EADI
EIF
TF
ADF
¾
Function
Controls the master (global) interrupt (1= enable; 0= disable)
Controls the external interrupt (1= enable; 0= disable)
Controls the Timer/Event Counter interrupt (1= enable; 0= disable)
Control the A/D converter interrupt (1= enable; 0= disable)
External interrupt request flag (1= active; 0= inactive)
Internal Timer/Event Counter request flag (1= active; 0= inactive)
A/D converter request flag (1= active; 0= inactive)
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC (0BH) Register
Rev. 1.00
10
August 24, 2006
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