HT46R54A 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT46R54A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R53A/HT46R54A

The lower byte of the PC (PCL) is a readable and

writeable register (06H). Moving data into the PCL per-

forms a short jump. The destination is within 256 loca-

tions.

When a control transfer takes place, an additional

dummy cycle is required.

Program Memory - EPROM

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

2048´15 (HT46R53A), or 4096´15 (HT46R54A) bits,

addressed by the Program Counter and table pointer.

Certain locations in the ROM are reserved for special

usage:

· Location 000H

This location is reserved for program initialization. Af-

ter a chip reset, the program always begins execution

at location 000H.

000H

004H

008H

00C H

010H

014H

018H

D e v ic e In itia liz a tio n P r o g r a m

E x te r n a l In te r r u p t S u b r o u tin e

T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e

A /D C o n v e r te r In te r r u p t S u b r o u tin e

P ro g ra m

M e m o ry

· Location 004H

This location is reserved for the external interrupt ser-

vice program. If the INT input pin is activated, the in-

terrupt is enabled and the stack is not full, the program

begins execution at this location.

· Location 008H

This location is reserved for the timer/event counter

interrupt service program. If a timer interrupt results

from a timer/event counter overflow, and the interrupt

is enabled and the stack is not full, the program begins

execution at location 008H.

· Location 00CH

Location 00CH is reserved for the A/D converter inter-

rupt service program. If an A/D converter interrupt re-

sults from an end of A/D conversion, and if the

interrupt is enabled and the stack is not full, the pro-

gram begins execution at location 00CH.

· Table location

Any location in the program memory can be used as

look-up tables. The instructions ²TABRDC [m]² (the

current page) and ²TABRDL [m]² (the last page) trans-

000H

004H

008H

00C H

010H

014H

018H

D e v ic e In itia liz a tio n P r o g r a m

E x te r n a l In te r r u p t S u b r o u tin e

T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e

A /D C o n v e r te r In te r r u p t S u b r o u tin e

P ro g ra m

M e m o ry

n00H

nFFH

L o o k - u p T a b le ( 2 5 6 w o r d s )

n00H

nFFH

L o o k - u p T a b le ( 2 5 6 w o r d s )

700H

L o o k - u p T a b le ( 2 5 6 w o r d s )

7FFH

1 5 b its

H T46R 53A

N o te : n = 0 ~ 7

F00H

FFFH

Program Memory

L o o k - u p T a b le ( 2 5 6 w o r d s )

1 5 b its

H T46R 54A

N o te : n = 0 ~ F

Instruction

TABRDC [m]

TABRDL [m]

b11 b10 b9

P11 P10 P9

1

1

1

Table Location

b8 b7 b6 b5 b4 b3 b2 b1 b0

P8 @7 @6 @5 @4 @3 @2 @1 @0

1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

Note:

b11~b0: Table location bits

P11~P8: Current program counter bits

@7~@0: Table pointer bits

For the HT46R53A, since the program counter is 11 bits wide (b0~b10), the b11 columns in the table are not

applicable

For the HT46R54A, the TABRDC program counter is 12 bits wide. From b0~b11

Rev. 1.00

7

August 24, 2006

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