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HT46R53A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R53A/HT46R54A

fer the contents of the lower-order byte to the speci-

fied data memory, and the higher-order byte to TBLH

(08H). The lower-order byte table pointer TBLP (07H)

are read/write registers, which indicate the table loca-

tions. Before accessing the table, the location has to

be placed in TBLP. The TBLH is read only and cannot

be restored. If the main routine and the ISR (interrupt

service routine) both employ the table read instruc-

tion, the contents of the TBLH in the main routine are

likely to be changed by the table read instruction used

in the ISR. Errors can occur. Given this, using the ta-

ble read instruction in the main routine and the ISR si-

multaneously should be avoided. However, if the table

read instruction has to be applied in both main routine

and the ISR, the interrupt should be disabled prior to

the table read instruction. It will not be enabled until

the TBLH in the main routine has been backed-up. All

table related instructions require 2 cycles to complete

the operation.

Stack Register - STACK

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 6 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At the state of a subroutine call or an interrupt acknowl-

edgment, the contents of the program counter are

pushed onto the stack. At the end of the subroutine or an

interrupt routine, signaled by a return instruction (RET or

RETI), the program counter is restored to its previous

value from the stack. After a chip reset, the SP will point

to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt is

serviced. This feature prevents stack overflow, allowing

the programmer to use the structure more easily. If the

stack is full and a ²CALL² is subsequently executed,

stack overflow occurs and the first entry will be lost (only

the most recent 6 return addresses are stored).

Data Memory - RAM

The data memory (RAM) is designed with 217´8 bits

(HT46R53A), 306´8 bits (HT46R54A), and is divided

into two functional groups, namely; special function reg-

isters (25´8 bits for HT46R53A, 26´8 bits for

HT46R54A) and general purpose data memory

(192´8bit for HT46R53A, 280´8bit (Bank0 216´8 bits

and Bank1 64´8 bits) for HT46R54A) most of which are

readable/writable, although some are read only.

In case of HT46R53A, the unused space before 28H is

reserved for future expanded usage and reading these

locations will return the result ²00H². The general pur-

pose data memory, addressed from 28H to E7H, is used

for data and control information under instruction com-

mands. All of the data memory areas can handle arith-

metic, logic, increment, decrement and rotate

operations directly. Except for some dedicated bits,

each bit in the data memory can be set and reset by

²SET [m].i² and ²CLR [m].i². They are also indirectly ac-

cessible through memory pointer registers (MP0;01H or

MP1;03H).

In case of HT46R54A, the unused space before 28H is

reserved for future expanded usage and reading these

locations will return the result ²00H². The space before

40H is overlapping in each bank. The general purpose

data memory, addressed from 28H to FFH (Bank0;

BP=00H) and from 40H to 7FH (Bank1; BP=01H), are

used for data and control information under instruction

commands. All of the data memory areas can handle

arithmetic, logic, increment, decrement and rotate oper-

ations directly. Except for some dedicated bits, each bit

in the data memory can be set and reset by ²SET [m].i²

and ²CLR [m].i². They are also indirectly accessible

through memory pointer registers (MP0;01H or

MP1;03H). After first setting up BP to the value of ²01H²

to access Bank1, this bank must then be accessed indi-

rectly using the memory pointer MP1. With BP set to a

value of ²01H², using MP1 to indirectly read or write to

the data memory areas with addresses at 40H will result

in operations to Bank1. Directly addressing the data

memory will always result in Bank0 being accessed irre-

spective of the value of BP.

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] ([02H]) will access the data memory

pointed to by MP0 (MP1). Reading location 00H (02H)

itself indirectly will return the result ²00H². Writing indi-

rectly results in no operation. The memory pointer regis-

ters (MP0 and MP1) are 8-bit registers.

Accumulator - ACC

The accumulator closely relates to ALU operations. It is

also mapped to location ²05H² of the data memory

which can operate with immediate data. The data move-

ment between two data memories has to pass through

the accumulator.

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic operations.

The ALU provides the following functions:

· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

Rev. 1.00

8

August 24, 2006

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