HT46R62 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT46R62 Datasheet PDF : 46 Pages
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HT46R62/HT46C62
Functional Description
Execution Flow
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is inter-
nally divided into four non-overlapping clocks. One in-
struction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each in-
struction to be effectively executed in a cycle. If an in-
struction changes the value of the program counter, two
cycles are required to complete the instruction.
Program Counter - PC
The program counter (PC) is 11 bits wide and it controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
specify a maximum of 2048 addresses.
After accessing a program memory word to fetch an in-
struction code, the value of the PC is incremented by 1.
The PC then points to the memory word containing the
next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading a PCL register, a subroutine call, an ini-
tial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise proceed to the next instruction.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Initial Reset
External Interrupt 0
External Interrupt 1
Timer/Event Counter Overflow
Time Base Interrupt
RTC Interrupt
Skip
Loading PCL
Jump, Call Branch
Return From Subroutine
Program Counter
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
Program Counter+2
*10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
#10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Note: *10~*0: Program counter bits
#10~#0: Instruction code bits
Program Counter
S10~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.60
7
July 14, 2005
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