HT46R63 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT46R63 Datasheet PDF : 44 Pages
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Pad Assignment
HT46C63
HT46R63/HT46C63
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
VSS
A N 0 /P B 0
A N 1 /P B 1
A N 2 /P B 2
A N 3 /P B 3
A N 4 /P B 4
A N 5 /P B 5
A N 6 /P B 6
A N 7 /P B 7
1
72
71
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
69 68 67 66 65 63 61 59 58
57
70
56
64 62 60
55
54
53
52
51
50
49
48
(0 , 0 )
47
46
45
44
43
42
41
40
39
38
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37
COM 1
COM 2
C O M 3 /S E G 1 9
S E G 18
S E G 17
S E G 16
S E G 15
S E G 14
S E G 13
S E G 12
S E G 11
S E G 10
SEG 9
SEG 8
SEG 7
SEG 6
SEG 5
SEG 4
SEG 3
SEG 2
SEG 1
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pin Description
Pin Name
PA0~PA7
PB0/AN0~
PB7/AN7
PC0~PC6,
PC7
PD0/PWM0~
PD3/PWM3,
PD4/INT0,
PD5/INT1,
PD6/TMR,
PD7
I/O
Option
Description
I/O
Pull-high
Wake-up
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PAC). Each line of PA can be optioned
as a wake-up input (bit option). I/O configurations: Schmitt trigger/CMOS
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
I/O Pull-High trolled by related control register bit (PBC). I/O configurations: Schmitt trig-
ger/CMOS. Each PB line is pin shared with an A/D converter input.
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
I/O Pull-High trolled by related control register bit (PCC). I/O configurations: Schmitt trig-
ger/CMOS.
I/O
Pull-High PWM
Interrupt Falling
and/or Rising
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PDC). I/O configurations: Schmitt trig-
ger/CMOS. The PD0~PD3 can be selected as PWM outputs. INT0/INT1
are falling/rising edge selectable triggers.
Rev. 1.90
4
May 17, 2004
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