HT46C65-56 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT46C65-56 Datasheet PDF : 48 Pages
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HT46R65/HT46C65
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 16 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledg-
ment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the program counter is restored to its
previous value from the stack. After chip reset, the SP
will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent sixteen return addresses are stored).
Data Memory - RAM
The data memory (RAM) is designed with 417´8 bits,
and is divided into two functional groups, namely; spe-
cial function registers 33´8 bit and general purpose data
memory, Bank0: 192´8 bit and Bank2: 192´8 bit most of
which are readable/writeable, although some are read
only. The special function register are overlapped in any
banks.
Of the two types of functional groups, the special func-
tion registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indi-
rect addressing register 1 (02H), a Memory pointer reg-
ister 1 (MP1;03H), a Bank pointer (BP;04H), an
Accumulator (ACC;05H), a Program counter
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), a Timer/Event
Counter 0 (TMR0H:0CH; TMR0L:0DH), a Timer/Event
Counter 0 control register (TMR0C;0EH), a Timer/Event
Counter 1 (TMR1H:0FH;TMR1L:10H), a Timer/Event
Counter 1 control register (TMR1C; 11H), Interrupt con-
trol register 1 (INTC1;1EH) , PWM data register
(PWM0;1AH, PWM1;1BH, PWM2;1CH, PWM3;1DH),
the A/D result lower-order byte register (ADRL;24H), the
A/D result higher-order byte register (ADRH;25H), the
A/D control register (ADCR;26H), the A/D clock setting
register (ACSR;27H), I/O registers (PA;12H, PB;14H,
PD;18H) and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The remaining space before the 40H is re-
served for future expanded usage and reading these lo-
0 0 H In d ir e c t A d d r e s s in g R e g is te r 0
01H
M P0
0 2 H In d ir e c t A d d r e s s in g R e g is te r 1
03H
M P1
04H
BP
05H
ACC
06H
PCL
07H
TB LP
08H
TB LH
09H
R TC C
0A H
STATU S
0B H
IN T C 0
0C H
TM R 0H
0D H
TM R 0L
0E H
TM R 0C
0FH
TM R 1H
10H
TM R 1L
11H
TM R 1C
12H
PA
13H
PAC
14H
PB
15H
PBC
16H
17H
18H
PD
19H
PDC
1A H
PW M 0
1B H
PW M 1
1C H
PW M 2
1D H
PW M 3
1E H
IN T C 1
1FH
20H
21H
22H
23H
24H
ADRL
25H
ADRH
26H
ADCR
27H
ACSR
28H
S p e c ia l P u r p o s e
D a ta M e m o ry
3FH
40H
G e n e ra l P u rp o s e
D a ta M e m o ry
(3 8 4 B y te s )
FFH
:U nused
R e a d a s "0 0 "
RAM Mapping
cations will get ²00H². The space before 40H is
overlapping in each bank. The general purpose data
memory, addressed from 40H to FFH (Bank0; BP=0 or
Bank2; BP=2), is used for data and control information
under instruction commands. All of the data memory ar-
eas can handle arithmetic, logic, increment, decrement
and rotate operations directly. Except for some dedi-
cated bits, each bit in the data memory can be set and
Rev. 1.80
9
July 14, 2005
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