HT6116-70 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT6116-70

CMOS 2K × 8-Bit SRAM

Holtek Semiconductor 

HT6116-70

(6) OE is continuously low (OE=VIL).

(7) DOUT is at the same phase of the write data of this write cycle.

(8) DOUT is the read data of the next address.

(9) If CS is low during this period, I/O pins are in the output state; then the data input

signals of the opposite phase to the outputs must not be applied to them.

(10) Transition is measured ± 500mV from the steady state.

Data Rentention Characteristics

(Ta=–40°C to +85°C)

Symbol

Parameter

Conditions

Min. Max. Unit

VDR

VDD for Data Retention

CS ≥ VDD-0.2V

2 5.5 V

ICCDR Data Retention Current

VDD=3V, CS ≥ VDD-0.2V

VIN ≥ VDD-0.2V or VIN ≤ 0.2V

—

50 µA

tCDR Chip Disable Data Retention Time See Retention Timing

0

— ns

tR

Operation Recovery Time

See Retention Timing

tRC* — ns

*tRC=Read Cycle Time

Low VDD Data Retention Timing

8

3rd July ’97

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