HT82V16 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT82V16 Datasheet PDF : 12 Pages
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HT82V16
Timing Diagrams
Timing Mode
A
B
C
D
Sensor Mode
CDS
CDS
CIS/SHA
CIS/SHA
Channel Mode
3-channel internally-defined and pixel-rate mux (00)
1-channel internally-defined mux (01)
3-channel internally-defined and pixel-rate mux (00)
1-channel internally-defined mux (01)
Mode A
P ix e l n
A n a lo g In p u t
tA D
tA D
P ix e l n + 1
tC 1 A
tC 1 C 2 A
tC 2 C 1 A
tC R A
C D S C LK 1
tC 2 A
C D S C LK 2
tN V P
tN V P
tS T L 1
A D C C LK
R
G
B
R
G
B
R
G
B
tC P
D 15~D 0
R (n -4 )
D 15~D 8
R (n -4 )
D 7~D 0
G (n -4 )
D 15~D 8
G (n -4 )
D 7~D 0
B (n -4 )
D 15~D 8
B (n -4 )
D 7~D 0
R (n -3 )
D 15~D 8
R (n -3 )
D 7~D 0
G (n -3 )
D 15~D 8
G (n -3 )
D 7~D 0
B (n -3 )
D 15~D 8
B (n -3 )
D 7~D 0
R (n -2 )
D 15~D 8
R (n -2 )
D 7~D 0
Note: DATA timing from pixel to pixel is decided by the first rising edge of ADCCLK when
CDSCLK2 is from high to low.
Mode B
A n a lo g In p u t
C D S C LK 1
P ix e l n
tA D
tC 1 B
tC 1 C 2 B
tA D
tC 2 C 1 B
P ix e l n + 1
tC R B
P ix e l n + 2
tC 2 B
C D S C LK 2
D 15~D 0
D (n -1 0 )
D 15~D 8
D (n -1 0 )
D 7~D 0
D (n -9 )
D 15~D 8
D (n -9 )
D 7~D 0
D (n -8 )
D 15~D 8
Rev. 1.10
5
June 7, 2001
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