HT82V26A 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT82V26A Datasheet PDF : 17 Pages
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HT82V26A
Functional Description
Integral Nonlinear (INL)
Integral nonlinear error refers to the deviation of each in-
dividual code from a line drawn from zero scale through
a positive full scale. The point used as zero scale occurs
1/2 LSB before the first code transition. A positive full
scale is defined as a level 1/2 LSB beyond the last code
transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinear (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation from this ideal value.
Thus every code must have a finite width. No missing
codes guaranteed for the 16-bit resolution indicates that
all the 65536 codes respectively, are present in the
over-all operating range.
Offset Error
The first ADC code transition should occur at a level 1/2
LSB above the nominal zero scale voltage.
The offset error is the deviation of the actual first code
transition level from the ideal level.
Gain Error
The last code transition should occur for an analog
value of 1/2 LSB below the nominal full-scale voltage.
Gain error is the deviation of the actual difference be-
tween the first and the last code transitions and the ideal
difference between the first and the last code transi-
tions.
Aperture Delay
The aperture delay is the time delay that occurs when a
sampling edge is applied to the HT82V26A until the ac-
tual sample of the input signal is held. Both CDSCLK1
and CDSCLK2 sample the input signal during the transi-
tion from high to low, so the aperture delay is measured
from each clock¢s falling edge to the instant the actual
internal sample is taken.
Internal Register Descriptions
Register
Address
Data Bits
Name
A2 A1 A0 D8 D7 D6 D5 D4
D3
D2
D1
D0
Configuration 0
0
0
0
0
1
3-CH
CDS
on
Clamp
Voltage
Enable
Power
Down
Output
Delay
1 byte out
MUX
0
0
1
0
RGB/
BGR
Red Green Blue
Delay CDSCLK1 CDSCLK2 ADCCLK
enable delay delay delay
Red PGA
0
1
0
0
0
0 MSB
LSB
Green PGA 0
1
1
0
0
0 MSB
LSB
Blue PGA
1
0
0
0
0
0 MSB
LSB
Red Offset
1
0
1 MSB
LSB
Green Offset 1 1 0 MSB
LSB
Blue Offset 1 1 1 MSB
LSB
Internal Register Map
Configuration Register
The configuration register controls the HT82V26A¢s operating mode and bias levels. Bits D6 should always be set high.
Bit D5 will configure the HT82V26A for the 3-channel (high) mode of operation. Setting the bit D4 high will enable the
CDS mode of operation, and setting this bit low will enable the SHA mode of operation.
Bit D3 sets the dc bias level of the HT82V26A¢s input clamp. This bit should always be set high for the 4V clamp bias,
unless a CCD with a reset feed through transient exceeding 2V is used. Setting the bit D3 low, the clamp voltage is 3V.
Bit D2 controls the power-down mode. Setting bit D2 high will place the HT82V26A into a very low power ²sleep² mode.
All register contents are retained while the HT82V26A is in the power-down state. Setting bit D1 high will configure the
HT82V26A for the digital output (D0~D7) delay 2ns. Bit D0 controls the output mode of the HT82V26A. Setting bit D0
high will enable a single byte output mode where only 8 MSBs of the 16b ADC is output. If bit D0 is set low, then the 16b
ADC output is multiplexed into two bytes.
Rev. 1.00
6
August 16, 2005
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