HT82V42 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT82V42 Datasheet PDF : 24 Pages
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HT82V42
Offset Registers
There are three offset registers used to individually program the offset. Bits D7 through D0 control the offset range from
-315mV to 315mV in 256 increments.
The Table shows the offset range as a function of the bits D7 through D0.
D7
D6
D5
D4
D3
D2
D1
D0
Offset
MSB
LSB
(mV)
0
0
0
0
0
0
0
0
-315
:
:
:
:
1
0
0
0
0
0
0
0*
0
:
:
:
:
1
1
1
1
1
1
1
1
+315
Note :*Power-on default value
Offset Register Settings
ADC Input Black Level Adjust
The output from the PGA should be offset to match the
full-scale range of the ADC (VFS=2.0V). For nega-
tive-going input video signals, a black level (zero differ-
ential) output from the PGA should be offset to the top of
the ADC range by setting register bits PGAFS[1:0]=10.
For positive going input signal the black level should be
offset to the bottom of the ADC range by setting
PGAFS[1:0]=11. Bipolar input video is accommodated
by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero dif-
ferential input voltage gives mid-range ADC output).
Overall Signal Flow Summary
The input sampling block produces an effective input
voltage V1. For CDS, this is the difference between the
input video level VIN and the input reset level VRESET.
For non-CDS this is the difference between the input
video level VIN and the voltage on the VRLC/VBIAS pin,
VVRLC, optionally set via the RLC DAC.
The offset DAC block then adds the amount of fine offset
adjustment required to move the black level of the input
signal towards 0V, producing V2.
The PGA block then amplifies the white level of the input
signal to maximise the ADC range, outputting voltage
V3.
The ADC block then converts the analogue signal, V3,
to a 16-bit unsigned digital output, D1. The digital output
is then inverted, if required, through the output invert
block to produce D2.
Calculating Output for any Given Input
The following equations describe the processing of the
video and reset level signals through the HT82V42. The
values of V1, V2 and V3 are often calculated in reverse
order during device setup. The PGA value is written first
to set the input Voltage range, the Offset DAC is then
adjusted to compensate for any Black/Reset level off-
sets and finally the RLC DAC value is set to position the
reset level correctly during operation.
Rev. 1.20
Overall Signal Flow
10
December 8, 2010
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