Control Interface Timing
Symbol
Parameter
SCYC
SLO
SHI
SSU
SH
SR
SF
SNUM
SCK Clock Frequency
SCK Clock Low Level Width
SCK Clock High Level Width
Data Setup Time Period
Data hold Time Period
SCK, CS Rising Time Period
SCK, CS Falling Time Period
Number of Serial Data
Test Conditions
VDD Conditions
3.0V
¾
3.0V
¾
3.0V
¾
3.0V
¾
3.0V
¾
3.0V 30%®70%
3.0V 70%®30%
3.0V
¾
HT82V842
VSS=0V, Ta=25°C)
Min. Typ. Max. Unit
¾
¾
10 MHz
40
¾
¾
ns
40
¾
¾
ns
20
¾
¾
ns
20
¾
¾
ns
¾
¾
6
ns
¾
¾
6
ns
¾
16
¾
pcs
CS
S SU
S CYC
SH
S LO
S HI
SCK
SD ATA
S SU
SH
O0
O1
A 0 ...
D8
D9
S NUM
Serial I/F Timing Chart
Data Output Sequence
CCD
0
1
2
3
4
5
6
7
8
SHR
SHD
50% V DD
50% V DD
50% V DD
ADCK
O U TC K
B LK
D O 0~ D O 9
B la c k L e v e l C o d e
0
1
2
3
Pixel Data Readout Sequence (1): Start of Conversion
Rev. 1.00
13
July 15, 2004