HT82V842 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT82V842

CCD CDS/PGA/10b-20M-ADC

Holtek Semiconductor 

HT82V842

CCD

(N -1 ) N

SHR

SHD

ADCK

O U TC K

B LK

D O 0~ D O 9

N -8 N -7 N -6 N -5 N -4 N -3 N -2 N -1

N

Pixel Data Readout Sequence (2): End of Conversion

B la c k L e v e l C o d e

Clock Timing Variations by Register Setting

Clock timing variations when it is inverted by register settings.

· No inversion

Mode 1 register D6=0, Mode 2 register D2=0; Default

CCD

SHR

SHD

ADCK

O U TC K

D O 0~ D O 9

Pulse Control (Default: No Inversion)

Rev. 1.00

14

July 15, 2004

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