HT82V842 데이터 시트보기 (PDF) - Holtek Semiconductor

부품명

상세내역

제조사

HT82V842

CCD CDS/PGA/10b-20M-ADC

Holtek Semiconductor 

HT82V842

Functional Description

CDS (Correlated Double Sampling) Circuit

Connect the CCDIN pin to the CCD sensor thru a capac-

itor. Connect also the REFIN pin to VSS thru a capacitor.

The CDS circuit holds the pre-charge voltage of the

CCD at SHR pulse and do sampling of the CCD pixel

data at SHD pulse. Correlated noise is removed by sub-

tracting the pre-charge voltage from the pixel data level.

CDS could choose a gain setting from 0, 6.02, 12 or

-1.94dB (Mode 3, register D4 and D5 bits). A CDS gain

is controlled by PGA gain. It is recommended to in-

crease the CDS gain then increase the PGA gain to re-

duce the noise level.

Clamp Circuits

· DC clamp

The DC level of the CCDIN/REFIN input is fixed by an

internal DC clamp circuit. The DC level of the

C-coupled CCD signal at the CDS input is set to

CLPCAP by the internal DC clamp circuit. The clamp

switches are usually turned on at the black level cali-

bration period. The CLPCAP pin connects to VSS thru

a 0.1mF capacitor.

· ADIN signal clamp

Clamp operation can also be used for the ADIN path.

The clamp voltage is different from the CCDIN/REFIN

signal and it could be turned off by register setting. At

²ADIN signal to ADC² mode, the ADCLP signal con-

trols the ²clamp circuit². Black level calibration circuit

is also controlled by ADCLP at ²ADIN signal to PGA²

mode.

· Clamp control

¨ Clamp current (Mode 2 register D7). Charge current

can select normal or fast clamp.

CCD

¨ Clamp target (Mode 2 register D5 and D4), input

signals (REFIN and CCDIN) to be clamped are

selectable. The clamp function can be turned off.

Black Level Cancel Circuit

The purpose of a black level cancel circuit is to control

the DC level of the PGA input. The ADC output code at

an optical black period may correspond to the black

level code set up by the register. A black level code of (1

to) 16 to 127 LSB is available (the default is 64 LSB).

While the OBP pin is active a black level cancel loop is

established. In the loop, a comparison is made between

the ADC output code and the black level code, the result

controls the voltage of the OBCAP capacitor. Hence, the

OBCAP voltage settles gradually and the signal level of

the optical black period corresponds to the established

value.

The following conditions will reset the OBCAP capaci-

tor:

· Set the black level reset register to ²1² (Mode 1 regis-

ter D1=1).

· Set the RESET pin to low

· Power down by STBY pin or register control

The DC clamping (CCDCLP) is allowed while the OBP

pin is low. The black level cancellation is available at

²ADIN signal to PGA² mode. The black level cancella-

tion is available at the ADCLP period in this mode. The

clamping function and black level canceling function are

done simultaneously.

ADCK

OB

E ffe c tiv e P ix e l

B la n k in g

B LK

O BP

C C D C LP

O U TC K

D O 0~ D O 9

Rev. 1.00

D a ta O u tp u t

5

B la c k C o d e

July 15, 2004

Share Link: