HT82K94A(2005) 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT82K94A
(Rev.:2005)

USB Multimedia Keyboard Encoder 8-Bit MCU

Holtek Semiconductor 

HT82K94E/HT82K94A

Program Memory - ROM

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

4096´15 bits, addressed by the program counter and ta-

ble pointer.

Certain locations in the program memory are reserved

for special usage:

· Location 000H

This area is reserved for program initialization. After

chip reset, the program always begins execution at lo-

cation 000H.

· Location 004H

This area is reserved for the USB and external inter-

rupt service program. If the USB interrupt or PA4/EXT

is activated, the interrupt is enabled and the stack is

not full, the program begins execution at location

004H.

There are EXTIF bit in register USR to indicate the ex-

ternal interrupt is activated.

· Location 008H

This area is reserved for the Timer/Event Counter 0 in-

terrupt service program. If a timer interrupt results

from a Timer/Event Counter 0 overflow, and if the in-

terrupt is enabled and the stack is not full, the program

begins execution at location 008H.

000H

D e v ic e In itia liz a tio n P r o g r a m

004H

U S B & E X T In te r r u p t S u b r o u tin e

008H

T im e r /E v e n t C o u n te r 0

In te r r u p t S u b r o u tin e

00C H

T im e r /E v e n t C o u n te r 1

In te r r u p t S u b r o u tin e

n00H

L o o k - u p T a b le ( 2 5 6 w o r d s )

nFFH

P ro g ra m

M e m o ry

1700H

17FFH

L o o k - u p T a b le ( 2 5 6 w o r d s )

1 6 b its

N o te : n ra n g e s fro m 0 to F

Program Memory

· Location 00CH

This location is reserved for the Timer/Event Counter

1 interrupt service program. If a timer interrupt results

from a Timer/Event Counter 1 overflow, and the inter-

rupt is enabled and the stack is not full, the program

begins execution at location 00CH.

· Table location

Any location in the program memory can be used as

look-up tables. There are three method to read the

ROM data by two table read instructions: ²TABRDC²

and ²TABRDL², transfer the contents of the

lower-order byte to the specified data memory, and

the higher-order byte to TBLH (08H).

The three methods are shown as follows:

¨ The instructions ²TABRDC [m]² (the current page,

one page=256words), where the table locations is

defined by TBLP (07H) in the current page. And the

ROM code option TBHP is disabled (default).

¨ The instructions ²TABRDC [m]², where the table lo-

cations is defined by registers TBLP (07H) and

TBHP (01FH). And the ROM code option TBHP is

enabled.

¨ The instructions ²TABRDL [m]², where the table lo-

cations is defined by Registers TBLP (07H) in the

last page (1700H~17FFH).

Only the destination of the lower-order byte in the ta-

ble is well-defined, the other bits of the table word are

transferred to the lower portion of TBLH, and the re-

maining 1-bit words are read as ²0². The Table

Higher-order byte register (TBLH) is read only. The ta-

ble pointer (TBLP, TBHP) is a read/write register (07H,

1FH), which indicates the table location. Before ac-

cessing the table, the location must be placed in the

TBLP and TBHP (If the OTP option TBHP is disabled,

the value in TBHP has no effect). The TBLH is read

only and cannot be restored. If the main routine and

the ISR (Interrupt Service Routine) both employ the

table read instruction, the contents of the TBLH in the

main routine are likely to be changed by the table read

instruction used in the ISR. Errors can occur. In other

words, using the table read instruction in the main rou-

tine and the ISR simultaneously should be avoided.

However, if the table read instruction has to be applied

in both the main routine and the ISR, the interrupt

should be disabled prior to the table read instruction.

Instruction

*12 *11 *10 *9

TABRDC [m] P12 P11 P10 P9

TABRDL [m] 1

1

1

1

Note: *12~*0: Table location bits

@7~@0: Table pointer bits

Table Location

*8 *7 *6 *5 *4 *3 *2 *1 *0

P8 @7 @6 @5 @4 @3 @2 @1 @0

1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

P12~P8: Current program counter bits when TBHP is disabled

TBHP register bit3~bit0 when TBHP is enabled

Rev. 1.00

7

November 22, 2005

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