HV219 데이터 시트보기 (PDF) - Supertex Inc
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HV219 Datasheet PDF : 8 Pages
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HV219
Power Up/Down Sequence
1)
Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for
applications powering GND of the IC with different voltages.
2)
Vsig must always be at or in between VPP and VNN or floating during power up/down transition.
3)
Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms.
Logic Truth Table
Data in the 8-bit Shift Register
LE CL
Output Switch State
D0 D1 D2 D3 D4 D5 D6 D7
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
L L OFF
H
L L ON
L
LL
OFF
H
LL
ON
L
LL
OFF
H
LL
ON
L
LL
OFF
H
LL
ON
L
LL
OFF
H
LL
ON
L
LL
OFF
H
LL
ON
L
LL
OFF
H
LL
ON
LLL
OFF
HL L
ON
XXXXXXXX H L
HOLD PREVIOUS STATE
X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1.
2.
3.
4.
5.
6.
The eight switches operate independently.
Serial data is clocked in on the L to H transition clock.
The switches go to a state retaining their present condition at the rising edge of the LE .
When LE is low, the shift register data flows through the latch.
Shift register clocking has no effect on the switch states if LE is high.
The clear input overrides all other inputs.
Logic Timing Waveform
DN - 1
DN
DN + 1
DATA
50%
50%
IN
LE
CLOCK
DATA
OUT
VOUTOFF
(TYP)
ON
50%
t SU
50%
t WLE
t SD
50%
th
t DD
50%
t OFF
90%
50%
t ON
10%
CLR
50%
50%
t WCL
5
A042705
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