HV623PG 데이터 시트보기 (PDF) - Supertex Inc
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HV623PG Datasheet PDF : 10 Pages
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When data has been loaded into all 32 outputs of all chips (top and
bottom of the display panel), the load count pin is pulsed. On its
rising transition, all output levels are reset to zero and all the data
in the input latches is transferred to a like number of comparator
latches, (thus leaving the data latches ready to receive new data
during the following operations). After the transfer, the load count
pin is brought low. This transition begins the events that convert
the binary data into a gray-shade level.
Gray-shade Conversion
1) The COUNT CLOCK is started. An external signal is applied
to the COUNT CLOCK pin, causing the counter on each chip
to increment from binary 000 0000 to 111 1111 (0 to 127).
2) At the same time, the VR voltage is applied to all chips, via
charging transistors, causing the HOLD CAPACITOR (CH) on
each output to experience a rise in voltage.
3) The logic control compares the count in the comparator latch
to the count clock. The gate voltage of Q1 and the output
voltage HVOUT will ramp up at the same rate as VR.
4) Once VR has reached the maximum voltage, then all the pixels
will be at the final value. (See Output Gray Scale Voltage.)
Output Voltage Variation
HV623
The output voltage of the HV623 is determined by the logic and
the ramp voltage VR. It is possible that the output voltage may be
coupled to an unacceptable level due to its adjacent outputs
through the panel. In order to solve this problem, internal logic
(refer to Output Stage Detail) is integrated in the IC to minimize
the effect.
Two external pins VCTL and RCTL allow the feasibility to control the
current flowing through Q . The V pin is connected to a voltage
2
CTL
source and the RCTL pin is connected to ground through a resistor
(2V and 56KΩ are used for a particular panel). The internal bias
circuit will drive the resistor to a voltage level that is equal to the
V voltage at steady state through an operational amplifier. The
CTL
current flowing through Q1 and Q2 will be limited to VCTRL/RCTRL.
This combination of V and R will reduce the output voltage
CTL
CTL
variation to less than ±0.2V of delta voltage for each gray shade,
independent of its adjacent output voltages.
12-131
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