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HV9980 데이터 시트보기 (PDF) - Supertex Inc

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HV9980
SUTEX
Supertex Inc SUTEX
HV9980 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
HV9980
Pin Description
Pin #
Name Description
1
REF1
Voltage reference inputs to the current sense comparators. For best noise immunity, connect an
7
REF2 RC filter at each of these pins referenced to the corresponding PGND pin. The filter can consist
10
REF3
of a 1.0nF low impedance capacitor and a 1.0kΩ resistor.
2
VDD1
Power supply inputs. For best noise immunity, bypass each of these pins to the corresponding
8
VDD2 PGND pin with a 0.1uF low impedance capacitor. The VDD pins must be tied together on the
11
VDD3
PCB.
3
CLK
Input to an external clock signal common to all three channels. Programs the switching frequency
of the power MOSFET outputs at 1/6 of the clock signal frequency.
4
PWMD1
9
PWMD2 Dedicated PWM dimming inputs for each individual LED string driver channel.
12
PWMD3
5
AGND Common return pin for CLK, POL and PWMD inputs.
6
POL
Must be connected to AGND.
13
PGND3
20
PGND2
Power return terminals for corresponding DRAIN outputs. The PGND and AGND pins must be
tied together on the PCB.
24
PGND1
14
CS3
Signal inputs to the current sense comparators. Connect these pins to the corresponding
19
CS2
RSENSE outputs directly when the slope compensation feature is not used. When the slope
compensation is needed, connect a capacitor between each RSENSE and its corresponding CS
23
CS1
pin, and connect a resistor between each CS pin and VDD.
15 RSENSE3
18
RSENSE2
Open source outputs of the switching power MOSFETs. Connect a current sense resistor
between each of the RSENSE pins and its corresponding PGND pin.
22 RSENSE1
16
DRAIN3
17
DRAIN2 Open drain outputs of the switching power MOSFETs.
21
DRAIN1
9

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