HV9982 데이터 시트보기 (PDF) - Supertex Inc
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HV9982 Datasheet PDF : 13 Pages
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HV9982
Electrical Characteristics (cont.)
Sym Parameter
Min Typ Max Units Conditions
PWM Dimming (PWMD1, PWMD2 and PWMD3)
VPWMD(lo) PWMD input low voltage
VPWMD(hi) PWMD input high voltage
RPWMD PWMD pull down resistor
*-
- 0.8 V ---
* 2.0 -
-
V ---
- 100 130 160 kΩ VPWMD = 5V
Gate (GATE1, GATE2 and GATE3)
ISOURCE
ISINK
TRISE
TFALL
DMAX
Gate short circuit current, sourcing
Gate sinking current
Gate output rise time
Gate output fall time
Maximum duty cycle
# 0.2 -
-
# 0.4 -
-
--
- 85
--
- 45
# - 91.7 -
Over Voltage Protection (OVP1, OVP2 and OVP3)
VOVP,rising
VOVP,HYST
Over voltage rising trip point
Over voltage hysteresis
* 4.5 5.0 5.5
- - 0.5 -
A
VGATE = 0V
A
VGATE = VDD
ns CGATE = 1.0nF
ns CGATE = 1.0nF
% ---
V OVP rising
V OVP falling
Current Sense (CS1, CS2 and CS3)
TBLANK Leading edge blanking
TDELAY Delay to output of gate
RDIS
Discharge resistance for slope
compensation
* 100 - 250 ns ---
*-
-
200
ns
100mV overdrive to the current
sense
*-
- 650 Ω Gate = Low
Internal Transconductance Opamp (Gm1, Gm2 and Gm3)
GB Gain bandwidth product
# - 1.0 - MHz 75pF capacitance at COMP pin
AV
VCM
VO
G
m
VOFFSET
Open loop DC gain
Input common-mode range
Output voltage range
Transconductance
Input offset voltage
- 65
-
-
dB Output open
# -0.3 - 3.0 V ---
# 0.7
-
VDD
V ---
- 500 600 700 μA/V ---
- -5.0 - 5.0 mV ---
IBIAS
Input bias current
# - 0.5 1.0 nA ---
Oscillator (CLOCK)
f
OSC1
Oscillator frequency
KSW
Oscillator divider ratio
TOFF
CLOCK low time
- - 500 - kHz F = 6.0MHz
CLOCK
# - 6.0 -
- ---
# 50
-
-
ns ---
TON
CLOCK high time
# 50
-
-
ns ---
V
CLOCK input high
CLOCK,HI
* 2.0 -
-
V ---
VCLOCK,LO CLOCK input low
*-
- 0.8 V ---
# Denotes specifications guaranteed by design.
* The specifications which apply over the full operating temperature range at 0OC < TA < +85OC are guaranteed by design and characterization.
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