HV9982 데이터 시트보기 (PDF) - Supertex Inc
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HV9982 Datasheet PDF : 13 Pages
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HV9982
a current (which is almost constant since the VDD voltage is
much larger than the voltage at the CS pin). This current
flows into the capacitor and produces a ramp voltage across
the capacitor. The voltage at the CS pin is then the sum of
the voltage across the capacitor and the voltage across the
current sense resistor, with the voltage across the capacitor
providing the required slope compensation. When the GATE
turns off, an internal pull down FET discharges the capacitor.
The 300Ω resistance of the internal FET will prevent the volt-
age at the CS pin from going all the way to zero.
Fig.1 Slope Compensation
-
CS
+
GATE
VDD
Rsc
Csc
Rcs
transconductance amplifiers with tri-state output, which are
used to close the feedback loops and provide accurate cur-
rent control. The compensation networks are connected at
the COMP pins (COMP1-3).
The output of the op-amps are buffered and connected to
the current sense comparators using 12:1 resistor dividers.
The outputs of the op-amps are controlled by the signal ap-
plied to the PWMD pins (PWMD1-3). When PWMD is high,
the output of the opamp is connected to the COMP pin.
When PWMD is low, the output is left open. This enables
the integrating capacitor to hold the charge when the PWMD
signal has turned off the gate drive. When the IC is enabled,
the voltage on the integrating capacitor will force the con-
verter into steady state almost instantaneously.
Linear Dimming
The minimum value of the voltage will instead be:
VCS,MIN
=
VDD
RSC
•
650Ω
The slope compensation capacitor is chosen so that it can
be completely discharged by the internal 300Ω FET at the
CS pin during the time the FET is off. Assuming the worst
case switch duty cycle of 92%,
CSC = 0.08
3 • 650Ω • f
S
Assuming a down slope of DS (A/ms) for the inductor cur-
rent, the current sense resistor and the slope compensation
resistor can be computed as:
RCS =
VDD - 1
13
•
1
DS • 106 • 0.92
2 • fS
+ IIN,pk
2 • VDD
RSC =
DS • 106 • CSC • RCS
Control of the LED Current
The LED currents in the HV9982 are controlled in a closed-
loop manner. The current references which set the three
LED currents are provided at the REF pins (REF1-3). This
reference voltage is compared to the voltage at the FDBK1-
3 pins which sense the LED currents in the three channels
using current sense resistors. HV9982 includes three 1MHz
Linear Dimming can be accomplished in the HV9982 by vary-
ing the voltages at the REF pins. Note that since the HV9982
is a peak current mode controller, it has a minimum on-time
for the GATE outputs. This minimum on-time will prevent the
converters from completely turning off even when the REF
pins are pulled to GND. Thus, linear dimming cannot accom-
plish true zero LED current. To get zero LED current PWM
dimming has to be used. Note that different signals can be
connected to the three REF pins if desired and they need not
be connected together.
Due to the offset voltage of the short circuit comparator as
well as the non-linearity of the X2 gain stage, pulling the
REF pin very close to GND would cause the internal short
circuit comparator to trigger and shut down the IC. To over-
come this, the output of the gain stage is limited to 125mV
(minimum), allowing the REF pin to be pulled all the way to
0V without triggering the short circuit comparator.
PWM Dimming
PWM dimming in the HV9982 can be accomplished in one of
two ways - true PWM dimming using TTL compatible square
wave sources at the PWMD pins (PWMD1-3) or an analog
control of PWM dimming by applying a 0 - 2.0V linear sig-
nal to the PWMD pins. The analog control of PWM dimming
helps the HV9982 to be backward compatible with CCFL
controllers. All three channels can be individually PWM
dimmed as desired.
The mode of PWM dimming is set using control pins S1 and
S2. The truth table for S1 and S2 control is given in Table 1.
It is recommended that the pins be connected to either VDD
or GND and not left unconnected.
7
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