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HYS72D128300GBR-5-B 데이터 시트보기 (PDF) - Infineon Technologies

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HYS72D128300GBR-5-B
Infineon
Infineon Technologies Infineon
HYS72D128300GBR-5-B Datasheet PDF : 45 Pages
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HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Overview
1
Overview
1.1
Features
• 184-pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for “1U” PC, Workstation and Server main
memory applications
• One rank 128M × 72 organization and two rank 256M × 72 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and +2.6(± 0.1 V) power supply for DDR400
• Built with DDR SDRAMs in 66-Lead TSOPII and FBGA 60 package
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Re-drive for all input signals using register and PLL devices.
• Serial Presence Detect with E2PROM
• Low Profile Modules form factor: 133.35 mm × 28.58 mm (1.1”) × 4.00 mm and 133.35 mm × 30.48 mm
(1.2”) × 4.00 mm
• Based on Jedec standard reference card layout RawCard “B”, “C“ and “D“
• Gold plated contacts
Table 1 Performance
Part Number Speed Code
5
6
7
7F
Unit
Speed Grade
Component
DDR400B DDR333B DDR266A DDR266
Module
PC3200–3033 PC2700–2533 PC2100–2033 PC2100–2022 —
max. Clock Frequency @ CL = 3 fCK3 200
166
MHz
@ CL = 2.5 fCK2.5 166
166
143
143
MHz
@ CL = 2 fCK2 133
133
133
133
MHz
1.2
Description
The HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B are low profile versions of the standard
Registered DIMM modules with 1.1” inch (28.58) and 1.2” inch (30,40 mm) height for 1U Server Applications. The
Low Profile DIMM versions are available as 128M × 72 (1 GB) and 256M × 72 (2 GB).
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors
are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Data Sheet
6
Rev. 0.5, 2003-12

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