ICL7116CM44 데이터 시트보기 (PDF) - Intersil
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ICL7116CM44 Datasheet PDF : 14 Pages
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ICL7116, ICL7117
V+
V+
BP
ICL7116
DECIMAL
POINT
SELECT
TO LCD
DECIMAL
POINTS
TEST
CD4030
GND
FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE
HOLD Reading Input
The HLDR input will prevent the latch from being updated
when this input is at logic “1”. The chip will continue to make
A/D conversions, however, the results will not be updated to
the internal latches until this input goes low. This input can be
left open or connected to TEST (ICL7116) or GROUND
(ICL7117) to continuously update the display. This input is
CMOS compatible, and has a 70kΩ (See Figure 7) typical
resistance to either TEST (ICL7116) or GROUND (ICL7117).
Digital Section
Figures 7 and 8 show the digital section for the ICL7116 and
ICL7117, respectively. In the ICL7116, an internal digital
ground is generated from a 6V Zener diode and a large
P-Channel source follower. This supply is made stiff to absorb
the relative large capacitive currents when the back plane
(BP) voltage is switched. The BP frequency is the clock fre-
quency divided by 800. For three readings/second this is a
60Hz square wave with a nominal amplitude of 5V. The seg-
ments are driven at the same frequency and amplitude and
are in phase with BP when OFF, but out of phase when ON. In
all cases negligible DC voltage exists across the segments.
Figure 8 is the Digital Section of the ICL7117. It is identical
to the ICL7116 except that the regulated supply and back
plane drive have been eliminated and the segment drive has
been increased from 2mA to 8mA, typical for instrument size
common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
In both devices, the polarity indication is “on” for negative
analog inputs. If IN LO and IN HI are reversed, this indication
can be reversed also, if desired.
a
a
a
a
f bf bf b
gc
g
g
b
ec ecec
d
d
d
BACKPLANE
21
LCD PHASE DRIVER
TYPICAL SEGMENT OUTPUT
V+
0.5mA
2mA
SEGMENT
OUTPUT
INTERNAL DIGITAL GROUND
† THREE INVERTERS
ONE INVERTER SHOWN
FOR CLARITY
7
SEGMENT
DECODE
7
SEGMENT
DECODE
7
SEGMENT
DECODE
LATCH
1000’s
100’s
10’s
1’s
COUNTER COUNTER COUNTER COUNTER
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
CLOCK
†
÷4
LOGIC CONTROL
INTERNAL
DIGITAL
GROUND
70kΩ
VTH = 1V
40
OSC 1
39
OSC 2
38
OSC 3
1
HLDR
÷200
35
V+
6.2V
500Ω
TEST
37
26
V-
FIGURE 7. ICL7116 DIGITAL SECTION
8
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