ICS1524M 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS1524M

Dual Output Phase Controlled SSTL_3/PECL Clock Generator

Integrated Circuit Systems 

ICS1524

Document Revision History

Rev A

ICS1523 Rev T Datasheet used as a starting template

New Block Diagram substituted for old 1523 one

Removed reference to CLK / 2 Functionality

Created a set of clock outputs that bypass the DPA

External PDEN is now the IN-SEL MUX control bit

Text descriptions changed to support new 1524 block diagram

Rev B

Replaced page 15 “Layout Guidelines”

Replaced SIOC Package diagram on page 22

“Advanced Status” removed

Redrew front page graphics for clairity

Rev C

Corrected Chip Revision and Chip Version values on page 5

Changed Title on Page 1

Minor format changes to pages 8 and 21

Corrected pin names on page 10

ICS1524 Rev C 01/31/2003

2

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