ICS307G-03 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS307G-03 Datasheet PDF : 12 Pages
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ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Table 8. Miscellaneous Control Bits
Bit
24~88
110
111
112
122
123
124
125
126
129
130
131
Function
Reserved—set to 0
OE1—set to 1 to enable CLK1
OE2—set to 1 to enable CLK2
1 = Normal Operation, 0 = power down feedback counter, charge pump and VCO
Crystal Input = 1, Clock Input = 0
Selects source for CLK2 (see block diagram)
Selects source for CLK3 (see block diagram)
Reserved—set to 0
Reserved—set to 0
OE3—set to 1 to enable CLK3
Reserved—set to 0
Reserved—set to 0
External Components
The ICS307-03 requires a minimum number of external components for proper operation.
Decoupling Capacitors
TheICS307-03 requires 0.01µF decoupling capacitors to be connected between each VDD pin and the Ground
Plane. The 0.01µF capacitors must be placed as close to the ICS307-03’s power pins as possible to minimize lead
inductance.
Output Termination
The ICS307-03 has advanced output pads that allows the device to achieve very high speed (270 MHz) operation
with single ended clock outputs. The clock outputs on the ICS307-03 are designed to be directly connected to a 50
Ohm transmission line without the need for any series resistors.
Crystal Selection
A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of 12 C should be used. For
crystals with a specified load capacitance greater than 12, additional crystal capacitors may be connected from
each of the pins X1 and X2 to ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal
caps should be = (CL-12)*2, where CL is the crystal load capacitance in pF and C is the capacitance value from
Table 4.
For a single ended clock input, connect it to X1 and leave X2 unconnected with no capacitors on either pin.
MDS 307-03 C
7
Revision 101705
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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