ICS8308AGI 데이터 시트보기 (PDF) - Integrated Circuit Systems

부품명

상세내역

제조사

ICS8308AGI

LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8308I

LOW SKEW, 1-TO-8

DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

TABLE 1. PIN DESCRIPTIONS

Number

1, 11, 13, 15,

17, 19, 21, 23

Name

Q0, Q1, Q7, Q6,

Q5, Q4,Q3, Q2

Type

Output

Description

Clock outputs. LVCMOS / LVTTL interface levels.

2, 10, 14, 18, 22

3

GND

CLK_SEL

Power

Input

Pullup

Power supply ground.

Clock select input. Selects LVCMOS clock input

when HIGH. Selects CLK, nCLK inputs when LOW.

LVCMOS / LVTTL interface levels.

4

LVCMOS_CLK

Input Pullup Clock input. LVCMOS / LVTTL interface levels.

5

CLK

Input Pullup Non-inverting differential clock input.

6

nCLK

Input Pulldown Inverting differential clock input.

7

CLK_EN

Input Pullup Clock enable. LVCMOS / LVTTL interface levels.

8

OE

Input Pullup Output enable. LVCMOS / LVTTL interface levels.

9

VDD

Power

Core supply pin.

12, 16, 20, 24

VDDO

Power

Output supply pins.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

CIN

CPD

R

PULLUP

RPULLDOWN

ROUT

Parameter

Input Capacitance

Power Dissipation Capacitance

(per output)

Input Pullup Resistor

Input Pulldown Resistor

Output Impedance

Test Conditions

Minimum

5

Typical

4

12

51

51

7

Maximum

12

Units

pF

pF

kΩ

kΩ

Ω

TABLE 3A. CLOCK SELECT FUNCTION TABLE

Control Input

CLK_SEL

0

1

Clock Input

CLK, nCLK is selected

LVCMOS_CLK is selected

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

CLK_SEL LVCMOS_CLK

CLK

nCLK

Outputs

Q0:Q7

Input to Output Mode

Polarity

0

—

0

1

LOW Differential to Single Ended Non Inverting

0

—

1

0

HIGH Differential to Single Ended Non Inverting

0

—

0

Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting

0

—

1

Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting

0

—

Biased; NOTE 1

0

HIGH Single Ended to Single Ended Inverting

0

—

Biased; NOTE 1

1

LOW Single Ended to Single Ended Inverting

1

0

—

—

LOW Single Ended to Single Ended Non Inverting

1

1

—

—

HIGH Single Ended to Single Ended Non Inverting

NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".

8308AGI

www.icst.com/products/hiperclocks.html

2

REV. B JULY 25, 2005

Share Link: