ICS84326AM 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS84326AM

CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

PRELIMINARY

ICS84326

CRYSTAL-TO-3.3V LVPECL

SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS84326 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VCC, VCCA and VCCO

should be individually connected to the power supply plane

through vias, and bypass capacitors should be used for each

pin. To achieve optimum jitter performance, power supply iso-

lation is required. Figure 1 illustrates how a 20Ω resistor along

with a 10µF and a .01µF bypass capacitor should be con-

nected to each V pin.

CCA

VCC

VCCA

3.3V

.01µF 20 Ω

.01µF

10 µF

FIGURE 1. POWER SUPPLY FILTERING

TERMINATION FOR 3.3V LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

tion for 3.3V LVPECL outputs. The two different layouts

mentioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, termi-

nating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

designed to drive 50Ω transmission lines. Matched impedance

techniques should be used to maximize operating

frequency and minimize signal distortion. Figures 2A and 2B

show two different layouts which are recommended only

as guidelines. Other suitable clock layouts may exist and it

would be recommended that the board designers simulate to

guarantee compatibility across all printed circuit and clock

component process variations.

Zo = 50Ω

FOUT

FIN

Zo = 50Ω

50Ω

1

RTT =

Zo

(V + V / V –2) –2

OH

OL CC

50Ω

RTT

VCC - 2V

FIGURE 2A. LVPECL OUTPUT TERMINATION

FOUT

5

2 Zo

Z

o

=

50Ω

3.3V

5

2 Zo

FIN

Zo = 50Ω

3

2

Z

o

3

2 Zo

FIGURE 2B. LVPECL OUTPUT TERMINATION

84326AM

www.icst.com/products/hiperclocks.html

7

REV. A MARCH 10, 2003

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