ICS9169C-36 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9169C-36 Datasheet PDF : 5 Pages
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ICS9169C-36
Electrical Characteristics at 3.3V
VDD = +3.0 V±10%, TA = 0 – 70° C unless otherwise stated
AC Characteristics
PARAMETER
Input Clock Rise Time1
Input Clock Fall Time1
Rise time1 SREF0 output
Slew SREF0 Rising1
Fall time1 SREF0 output
Slew SREF0 Falling1
Rise time1 other outputs
Fall time1 other outputs
Duty cycle1
Jitter, one sigma1,2
Jitter, absolute1,2
Jitter, absolute1,2
Jitter, absolute1,2
Input Frequency1
Normal output frequency
Ratio of Nominal frequency
to target frequency1
Clock skew between
AUDIO/2 and
AUDIO outputs1
Power-up Time1
SYMBOL
tICr
tICf
tr1
Slew1
tf1
Slew2
tr2
tf2
dt
tjls1
tjab1
tjab2
tjab3
fin
FNOM
f/f
TEST CONDITIONS
45pF load, 0.8 to 2.0V
45pF 0.4 to 2.4V
45pF load, 0.8 to 2.0V
45pF 2.4 to 0.4V
20pF load, 0.8 to 2.0V
20pF load, 0.8 to 2.0V
25pF load at 1.5V (All outputs)
10,000 cycles (All outputs)
10,000 cycles 24, Audio, Audio/2
10,000 cycles 48MHz
10,000 cycles REF CLKS
with X1 driven at 14.31818MHz
48MHz
24MHz
33.86MHz
24.5795MHz
with X1 driven at 14.31818MHz
24.0MHz
48.0MHz
33.8688MHz
24.576MHz
Tsk
ttPO
to 33.8 MHz on Audio
MIN
-
-
0.3
0.8
0.3
0.8
0.6
0.6
45
-
750
-500
-3.5%
11
166
166
-200
-200
250
-
TYP
-
-
1.3
0.95
1.0
0.95
1.2
0.9
50
100
-
-
14.318
MAX
20
20
2.0
4.0
2.0
4.0
2.0
2.0
55
250
750
500
3.5
16
48.008MHz
24.004MHz
33.8650MHz
24.5795MHz
166.6
166.6
-23.6
+144
-
167
167
+200
+200
+250
5
10
UNITS
ns
ns
ns
V/ns
ns
V/ns
ns
ns
%
ps
ps
ps
%
MHz
MHz
ppm
ps
ms
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Note 2: Absolute Jitter is defined as largest difference of the shortest period to the mean or the longest period to the
mean in a sampling of 10,000 clock cycles. One Sigma Jitter is the calculated standard deviation.
4
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