IDT54FCT162841AT 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT54FCT162841AT

FAST CMOS 20-BIT TRANSPARENT LATCHES

Integrated Device Technology 

IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET

FAST CMOS 20-BIT TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT16841CT/162841CT

FCT16841ET/162841ET

Com'l.

Mil.

Com'l.

Mil.

Symbol

Parameter

Condition(1)

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

tPLH Propagation Delay

CL = 50pF

1.5 5.5 1.5 6.3 1.5 3.4

—

— ns

tPHL xDx to xQx

(LE = HIGH)

RL = 500Ω

CL = 300pF(5) 1.5 13.0 1.5 15.0 1.5

7.5

—

—

RL = 500Ω

tPLH Propagation Delay

CL = 50pF

1.5 6.4 1.5 6.8 1.5 3.7

—

— ns

tPHL xLE to xQx

RL = 500Ω

CL = 300pF(5) 1.5 15.0 1.5 16.0 1.5

7.5

—

—

RL = 500Ω

tPZH Output Enable Time

tPZL xOE to xQx

CL = 50pF

1.5 6.5 1.5 7.3 1.5 4.4

—

— ns

RL = 500Ω

CL = 300pF(5) 1.5 12.0 1.5 13.0 1.5

9.0

—

—

tPHZ Output Disable Time

tPLZ xOE to xQx

RL = 500Ω

CL = 5pF(5)

1.5 5.7 1.5 6.0 1.5 3.6

—

— ns

RL = 500Ω

CL = 50pF

1.5 6.0 1.5 6.3 1.5 3.6

—

—

RL = 500Ω

tSU Set-Up Time HIGH or LOW,

CL = 50pF

2.5

—

2.5

—

1.0

—

—

— ns

xDx to xLE

RL = 500Ω

tH

Hold Time HIGH or LOW,

2.5

—

2.5

—

1.0

—

—

— ns

xDx to xLE

tW

xLE Pulse Width HIGH

4.0(4)

—

4.0(4)

—

3.0(4)

—

—

— ns

tSK(o) Output skew(3)

—

0.5

—

0.5

—

0.5

—

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This limit is guaranteed but not tested.

5. This condition is guaranteed but not tested.

— ns

2556 tbl 10

5.18

7

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