IDT71256SA 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT71256SA Datasheet PDF : 8 Pages
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IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
tAA
OE
CS
DATAOUT
tOE
(5)
tOLZ
(3)
tACS
(5)
tCLZ
HIGH IMPEDANCE
VCC SUPPLY ICC
tPU
CURRENT
ISB
Commercial and Industrial Temperature Ranges
(5)
tOHZ
(5)
tCHZ
DATA OUT VALID
tPD
, 2948 drw 05
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC
ADDRESS
DATAOUT
tAA
tOH
PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
, 2948 drw 06
6.452
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