IDT71256SA15P 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT71256SA15P

CMOS STATIC RAM 256K (32K x 8-BIT)

Integrated Device Technology 

IDT71256SA

CMOS STATIC RAM 256K (32K x 8-BIT)

INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

tRC

ADDRESS

tAA

tOH

DATAOUT

PREVIOUS DATAOUT VALID

tOH

DATAOUT VALID

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

2948 drw 06

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,5)

ADDRESS

CS

WE

DATAOUT

DATAIN

tWC

tAW

tAS

tWP(3)

tWR

tWHZ (6)

tOW (6)

(4)

HIGH IMPEDANCE

tDH

tDW

DATAIN VALID

tCHZ (6)

(4)

2948 drw 07

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,5)

tWC

ADDRESS

tAW

CS

tAS

tCW

tWR

WE

tDW

tDH

DATAIN

DATAIN VALID

2948 drw 08

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn

off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the

minimum write pulse is as short as the specified tWP.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

5

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