IDT7130SA100C 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7130SA100C Datasheet PDF : 19 Pages
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IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(5)
7130X20(2)
7140X20(2)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
Write Cycle Time(3)
20
____
25
____
35
____
ns
tEW
Chip Enable to End-of-Write
15
____
20
____
30
____
ns
tAW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
tAS
Address Set-up Time
tWP
Write Pulse Width(4)
0
____
0
____
0
____
ns
15
____
15
____
25
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(1)
10
____
12
____
15
____
ns
____
10
____
10
____
15
ns
tDH
Data Hold Time
tWZ
Write Enable to Output in High-Z(1)
tOW
Output Active from End-of-Write(1)
0
____
0
____
0
____
ns
____
10
____
10
____
15
ns
0
____
0
____
0
____
ns
2689 tbl 10a
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Military
Symbol
Parameter
Min. Max. Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time(3)
55
____
100
____
ns
tEW
Chip Enable to End-of-Write
40
____
90
____
ns
tAW
Address Valid to End-of-Write
40
____
90
____
ns
tAS
Address Set-up Time
tWP
Write Pulse Width(4)
0
____
0
____
ns
30
____
55
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(1)
20
____
40
____
ns
____
25
____
40
ns
tDH
Data Hold Time
tWZ
Write Enable to Output in High-Z(1)
tOW
Output Active from End-of-Write(1)
0
____
0
____
ns
____
25
____
40
ns
0
____
0
____
ns
NOTES:
2689 tbl 10b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but
is not production tested.
2. PLCC, TQFP and STQFP packages only.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data
to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
10
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