IDT7130SA100FG 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7130SA100FG Datasheet PDF : 19 Pages
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IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7)
7130X20(1)
7140X20(1)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Symbol
Parameter
BUSY TIMING (For MASTER IDT 7130)
tBAA
BUSY Access Time from Address
tBDA
BUSY Disable Time from Address
tBAC
BUSY Access Time from Chip Enable
tBDC
BUSY Disable Time from Chip Enable
tWH
Write Hold After BUSY(6)
tWDD
Write Pulse to Data Delay(2)
tDDD
Write Data Valid to Read Data Delay(2)
tAPS
Arbitration Priority Set-up Time(3)
tBDD
BUSY Disable to Valid Data(4)
BUSY INPUT TIMING (For SLAVE IDT 7140)
tWB
Write to BUSY Input(5)
tWH
Write Hold After BUSY(6)
tWDD
Write Pulse to Data Delay(2)
tDDD
Write Data Valid to Read Data Delay(2)
Min.
Max.
Min.
Max.
Min.
Max. Unit
____
20
____
20
____
20
ns
____
20
____
20
____
20
ns
____
20
____
20
____
20
ns
____
20
____
20
____
20
ns
12
____
15
____
20
____
ns
____
40
____
50
____
60
ns
____
30
____
35
____
35
ns
5
____
5
____
5
____
ns
____
25
____
35
____
35
ns
0
____
0
____
0
____
ns
12
____
15
____
20
____
ns
____
40
____
50
____
60
ns
____
30
____
35
____
35
ns
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Military
2689 tbl 11a
Symbol
BUSY TIMING (For MASTER IDT 7130)
Parameter
Min.
Max.
Min.
Max. Unit
tBAA
BUSY Access Time from Address]
____
30
____
50
ns
tBDA
BUSY Disable Time from Address
____
30
____
50
ns
tBAC
BUSY Access Time from Chip Enable
____
30
____
50
ns
tBDC
BUSY Disable Time from Chip Enable
____
30
____
50
ns
tWH
Write Hold After BUSY(6)
20
____
20
____
ns
tWDD
Write Pulse to Data Delay(2)
____
80
____
120
ns
tDDD
Write Data Valid to Read Data Delay(2)
____
55
____
100
ns
tAPS
Arbitration Priority Set-up Time(3)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(4)
BUSY INPUT TIMING (For SLAVE IDT 7140)
____
55
____
65
ns
tWB
Write to BUSY Input(5)
0
____
0
____
ns
tWH
Write Hold After BUSY(6)
20
____
20
____
ns
tWDD
Write Pulse to Data Delay(2)
____
80
____
120
ns
tDDD
Write Data Valid to Read Data Delay(2)
____
55
____
100
ns
NOTES:
1. PLCC, TQFP and STQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. 'X' in part numbers indicates power rating (S or L).
2689 tbl 11b
12
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