IDT7130SA100FG 데이터 시트보기 (PDF) - Integrated Device Technology

부품명

상세내역

제조사

IDT7130SA100FG

HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

Integrated Device Technology 

IDT7130SA/LA and IDT7140SA/LA

High-Speed 1K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

Truth Tables

Truth Table I — Non-Contention Read/Write Control(4)

Inputs(1)

R/W

CE

OE

D0-7

Function

X

H

X

Z

Port Disabled and in Power-Down Mode, ISB2 or ISB4

X

H

X

Z

CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3

L

L

X

DATAIN Data on Port Written into Memory(2)

H

L

L

DATAOUT Data in Memory Output on Port(3)

H

L

H

Z

High Impedance Outputs

NOTES:

1. A0L – A10L • A0R – A10R.

2. If BUSY = L, data is not written.

3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.

4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE

2689 tbl 13

Truth Table II — Interrupt Flag(1,4)

Left Port

R/WL

CEL

OEL

A9L-A0L

INTL

R/WR

CER

L

L

X

3FF

X

X

X

X

X

X

X

X

X

L

X

X

X

X

L(3)

L

L

X

L

L

3FE

H(2)

X

X

NOTES:

1. Assumes BUSYL = BUSYR = VIH

2. If BUSYL = VIL, then No Change.

3. If BUSYR = VIL, then No Change.

4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE

Truth Table III — Address BUSY

Arbitration

Inputs

Outputs

CEL CER

A0L-A9L

A0R-A9R

BUSYL(1) BUSYR(1)

Function

X X NO MATCH

H

H

Normal

HX

MATCH

H

H

Normal

XH

MATCH

H

H

Normal

LL

MATCH

(2)

(2)

Write Inhibit(3)

NOTES:

2689 tbl 15

1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for

IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull

outputs. On slaves the BUSYX input internally inhibits writes.

2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs

of this port. 'H' if the inputs to the opposite port became stable after the address and

enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will

result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW

regardless of actual logic level on the pin. Writes to the right port are internally

ignored when BUSYR outputs are driving LOW regardless of actual logic level on

the pin.

16

Right Port

OER

A9R-A0R

X

X

L

3FF

X

3FE

X

X

INTR

Function

L(2) Set Right INTR Flag

H(3) Reset Right INTR Flag

X Set Left INTL Flag

X Reset Left INTL Flag

2689 tbl 14

Share Link: