IDT7140SA100F 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7140SA100F

HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

Integrated Device Technology 

IDT7130SA/LA and IDT7140SA/LA

High-Speed 1K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle No. 1, Either Side(1)

tRC

ADDRESS

tAA

tOH

tOH

DATAOUT

BUSYOUT

PREVIOUS DATA VALID

DATA VALID

tBDDH (2,3)

2689 drw 08

NOTES:

1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.

2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,

BUSY has no relationship to valid output data.

3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

Timing Waveform of Read Cycle No. 2, Either Side(3)

CE

OE

DATAOUT

ICC

CURRENT

ISS

tACE

tAOE (4)

tLZ (1)

tLZ (1)

tPU

50%

tHZ (2)

tHZ (2)

VALID DATA

tPD(4)

50%

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is deaserted first, OE or CE.

3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

2689 drw 09

9

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