IDT7134SA55JB 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7134SA55JB Datasheet PDF : 9 Pages
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IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
PIN CONFIGURATIONS(1,2)
WCEL
R/ L
A11L
A10L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O 2L
I/O 3L
I/O 4L
I/O 5L
I/O 6L
I/O 7L
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9 IDT7134 40
10 P48–1 39
11
12
13
&
C48–2
DIP
38
37
36
14
15
16
TOP
VIEW (3)
35
34
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
W VCCECR
R/ R
A11R
A10R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
7 6 5 4 3 2 52 51 50 49 48 47
8
1
46
9
45
10
44
11
43
12
42
13
IDT7134
J52-1
41
14
PLCC
40
15
TOP VIEW (3)
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
N/C
I/O7R
2720 drw 02
INDEX
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
6 5 4 3 2 48 47 46 45 44 43
7
1
42
8
41
9
40
10
39
IDT7134
11
L48-1
38
12
&
F48-1
37
13
LCC/Flatpack
36
14
TOP VIEW (3)
35
15
34
16
33
17
32
18
31
19 20 21 22 23 24 25 26 27 28 29 30
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
2720 drw 04
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of actual part-marking.
ABSOLUTE MAXIMUM RATINGS(1)
2720 drw 03
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to Ground
TA
Operating
Temperature
TBIAS Temperature
Under Bias
TSTG Storage
Temperature
PT(3) Power Dissipation
Com’l.
–0.5 to +7.0
0 to +70
–55 to +125
–55 to +125
1.5
Mil.
Unit
–0.5 to +7.0 V
–55 to +125 °C
–65 to +135 °C
–65 to +150 °C
1.5
W
IOUT DC Output Current
50
50
mA
2720 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or
10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+0.5V.
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions(2) Max. Unit
CIN
Input Capacitance
VIN = 3dv
11 pF
COUT Output Capacitance VOUT = 3dv 11 pF
2720 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V and from 3V to 0V.
6.04
2
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