LTC1434 데이터 시트보기 (PDF) - Linear Technology
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LTC1434 Datasheet PDF : 20 Pages
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OPERATION (Refer to Functional Diagram)
Having only the small MOSFET on with low load current
reduces switching and gate charge losses, hence boosting
efficiency. For the device to go into low current mode, two
conditions must be satisfied: the peak current of the
inductor should not exceed 260mA and the voltage at the
ITH pin should not exceed 0.6V. When either one of the
conditions is exceeded, the big MOSFET will be turned on
at the next clock cycle.
LTC1433/LTC1434
source connected to the PLLIN pin. The output of the
phase detector at the PLL LPF pin is also the control input
of the oscillator, which operates over a 0V to 2.4V range
corresponding to – 30% to + 30% in the oscillator’s center
frequency. When locked, the PLL aligns the turn-on of the
MOSFETs to the rising edge of the synchronizing signal.
When the PLLIN is left open, PLL LPF goes low, forcing the
oscillator to minimum frequency.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the rate of change of inductor current
during the on cycle decreases. This reduction means that
the P-channel MOSFETs will remain on for more than one
oscillator cycle since the ICOMP is not tripped. Further
reduction in input supply voltage will eventually cause the
P-channel MOSFET to be turned on 100%, i.e., DC. The
output voltage will then be determined by the input voltage
minus the voltage drop across the MOSFETs. Typically
under dropout, both the power MOSFETs are on since the
voltage on the ITH pin is greater than 0.6V.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC1434 to
allow the oscillator to be synchronized to an external
Power-On Reset
The POR pin is an open-drain output which pulls low when
the regulator is out of regulation. When the output voltage
rises to within 5% of regulation, a timer is started which
releases POR after 216 (65536) oscillator cycles. In shut-
down the POR output is pulled low.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator will be reduced to about 1/4.5 of its designed
rate. This low frequency allows the inductor current to
discharge, thereby preventing runaway. The oscillator’s
frequency will gradually increase to its designed rate when
the output voltage increases above 0.65V.
APPLICATIONS INFORMATION
The basic LTC1434 application circuit is shown in
Figure 1. External component selection is driven by the
load requirement and begins with the selection of COSC
and L. Next, the Schottky diode D1 is selected followed by
CIN and COUT.
COSC Selection for Operating Frequency
The LTC1433/LTC1434 use a constant frequency archi-
tecture with the frequency determined by an external
oscillator capacitor COSC. During the on-time, COSC is
charged by a fixed current plus an additional current
which is proportional to the output voltage of the phase
detector (VPLL LPF on LTC1434). When the voltage on the
COSC capacitor reaches 1.19V, it is reset to ground. The
process then repeats.
The value of COSC is calculated from the desired operating
frequency. Assume the phase-locked loop has no external
oscillator input, i.e. VPLL LPF = 0V.
( ) ( ) COSC
pF
=
1.37
104
– 11
Frequency kHz
A graph for selecting COSC vs Frequency is given in Figure
2. For the LTC1433, the expression above is also appli-
cable since its oscillator is internally set up to run at a
condition equal to VPLL LPF = 0V. Therefore when using the
graph for determining the capacitance value for the oscil-
lator frequency, the VPLL LPF = 0V curve should be used for
LTC1433.
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