IDT71V124SA10PH 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT71V124SA10PH
Integrated Device Technology
IDT71V124SA10PH Datasheet PDF : 8 Pages
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IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V124SA10 71V124SA12 71V124SA15 71V124SA20
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
tAA
tACS
tCL Z(1)
tCHZ(1)
tOE
tOLZ(1)
tOHZ(1)
tOH
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
10
____
12
____
15
____
20
____
ns
____
10
____
12
____
15
____
20
ns
____
10
____
12
____
15
____
20
ns
4
____
4
____
4
____
4
____
ns
0
5
0
6
0
7
0
8
ns
____
5
____
6
____
7
____
8
ns
0
____
0
____
0
____
0
____
ns
0
5
0
5
0
5
0
7
ns
4
____
4
____
4
____
4
____
ns
WRITE CYCLE
tWC
Write Cycle Time
10
____
12
____
15
____
20
____
ns
tAW
Address Valid to End-of-Write
7
____
8
____
10
____
12
____
ns
tCW
Chip Select to End-of-Write
7
____
8
____
10
____
12
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
tWP
Write Pulse Width
7
____
8
____
10
____
12
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
5
____
6
____
7
____
9
____
ns
tDH
Data Hold Time
0
____
0
____
0
____
0
____
ns
tOW(2)
Output Active from End-of-Write
3
____
3
____
3
____
4
____
ns
tWHZ(2)
Write Enable to Output in High-Z
0
5
0
5
0
5
0
8
ns
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
3873 tbl 08
4
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