IDT71V124SA10YI 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT71V124SA10YI

3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Integrated Device Technology 

IDT71V124SA, 3.3V CMOS Static RAM

1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Timing Waveform of Read Cycle No. 1(1)

ADDRESS

OE

CS

DATAOUT

tRC

tAA

tOE

tOLZ (5)

tCLZ(5)

tACS(3)

HIGH IMPEDANCE

Commercial and Industrial Temperature Ranges

tOHZ (5)

tCHZ(5)

DATAOUT VALID

.

3873 drw 05

Timing Waveform of Read Cycle No. 2(1, 2, 4)

ADDRESS

DATAOUT

tRC

tAA

tOH

PREVIOUS DATAOUT VALID

tOH

DATAOUT VALID

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

. 3873 drw 06

6.452

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