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IDT71V256SA10PZGI8 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT71V256SA10PZGI8
IDT
Integrated Device Technology IDT
IDT71V256SA10PZGI8 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
OE
CS
DATAOUT
tAA
tOE
t OLZ (2)
t ACS
t CLZ (2)
NOTES:
1. WE is HIGH for Read cycle.
2. Transition is measured ±200mV from steady state.
Commercial and Industrial Temperature Ranges
tOH
t OHZ (2)
t CHZ (2)
DATA VALID
, 3101 drw 06
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC
ADDRESS
DATAOUT
tAA
tOH
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 3(1,3,4)
CS
DATAOUT
tACS
tCLZ (5)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
tOH
DATA VALID
, 3101 drw 07
DATA VALID
t CHZ (5)
,
3101 drw 08
6.452

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