IDT71V3556SA100BGI 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT71V3556SA100BGI

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

Integrated Device Technology 

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

Address A [0:17]

CE1, CE2, CE2

R/W

CEN

ADV/LD

BWx

DQ

DQ

256x18 BIT

MEMORY ARRAY

Address

Control

DI DO

DQ

Clk

Control Logic

Clock

OE

TMS

TDI

TCK

TRST

(optional)

JTAG

(SA Version)

TDO

Recommended DC Operating

Conditions

Symbol

Parameter

Min. Typ. Max. Unit

VDD Core Supply Voltage

3.135 3.3

3.465

V

VDDQ I/O Supply Voltage

3.135 3.3

3.465

V

VSS Supply Voltage

0

0

0

V

VIH Input High Voltage - Inputs

2.0

____

VDD +0.3

V

VIH Input High Voltage - I/O

2.0

____ VDDQ +0.3(2) V

VIL Input Low Voltage

-0.3(1)

____

0.8

V

NOTES:

5281 tbl 04

1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

Mux

Sel

D

Output Register

Q

Gate

, 5281 drw 01b

Data I/O [0:15],

I/O P[1:2]

6.442

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