IDT71V3558SA100BQ 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT71V3558SA100BQ

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

Integrated Device Technology 

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration - 128K x 36, 119 BGA

1

2

3

4

5

6

7

A VDDQ

A6

A4

NC(2)

A8

A16

VDDQ

B NC

CE 2

A3

ADV/LD

A9

CE2

NC

C

NC

A7

A2

VDD

A12

A15

NC

D I/O16

I/OP3

VSS

NC

VSS

I/OP2

I/O15

E I/O17

F VDDQ

G I/O20

H I/O22

J VDDQ

I/O18

I/O19

I/O21

I/O23

VDD

VSS

VSS

BW3

VSS

VDD(1)

CE1

OE

NC(2)

R/W

VDD

VSS

VSS

BW2

VSS

VDD(1)

I/O13

I/O12

I/O11

I/O9

VDD

I/O14

VDDQ

I/O10

I/O8

VDDQ

K I/O24

I/O26

VSS

CLK

VSS

I/O6

I/O7

L I/O25

M VDDQ

I/O27

I/O28

BW4

VSS

NC

CEN

BW1

VSS

I/O4

I/O5

I/O3

VDDQ

N I/O29

I/O30

VSS

A1

VSS

I/O2

I/O1

P I/O31

I/OP4

VSS

A0

VSS

I/O0

I/OP1

,

R NC

A5

LBO

VDD

VDD(1)

A13

NC

T NC

NC

A10

A11

A14

NC

NC/ZZ(5)

U VDDQ NC/TMS(3) NC/TDI(3) NC/TCK(3) NC/TDO(3) NC/TRST(3,4) VDDQ

5281 drw 13A

Top View

Pin Configuration - 256K x 18, 119 BGA

1

2

3

4

5

6

7

A VDDQ

B NC

A6

CE2

A4

NC(2)

A8

A3

ADV/LD

A9

A16

VDDQ

CE2

NC

C NC

A7

A2

VDD

A13

A17

NC

D I/O8

NC

VSS

NC

VSS

I/O7

NC

E NC

I/O9

VSS

CE1

VSS

NC

I/O6

F VDDQ

NC

VSS

OE

VSS

I/O5

VDDQ

G NC

I/O10

BW2

NC(2)

VSS

NC

I/O4

H I/O11

NC

VSS

R/W

VSS

I/O3

NC

J VDDQ

VDD

VDD(1)

VDD

VDD(1)

VDD

VDDQ

K NC

I/O12

VSS

CLK

VSS

NC

I/O2

L I/O13

NC

VSS

NC

BW1

I/O1

NC

M VDDQ

I/O14

VSS

CEN

VSS

NC

VDDQ

N I/O15

NC

VSS

A1

VSS

I/O0

NC

P NC

I/OP2

VSS

A0

VSS

NC

I/OP1

R NC

T NC

U VDDQ

A5

LBO

VDD

VDD(1)

A12

NC

A10

A15

NC

A14

A11

, NC/ZZ(5)

NC/TMS(3) NC/TDI(3) NC/TCK(3) NC/TDO(3) NC/TRST(3,4) VDDQ

5281drw 13B

Top View

NOTES:

1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. G4 and A4 are reserved for future 8M and 16M respectively.

3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin T7 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).

6.472

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