IDT71V3559SA75BQ 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT71V3559SA75BQ
Integrated Device Technology
IDT71V3559SA75BQ Datasheet PDF : 28 Pages
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IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 119 BGA
1
2
3
4
5
6
7
A VDDQ
A6
A4
NC(3)
A8
A16
VDDQ
B NC
CE 2
A3
ADV/LD
A9
CE2
NC
C NC
A7
A2
VDD
A12
A15
NC
D I/O16
I/OP3
VSS
NC
VSS
I/OP2
I/O15
E I/O17
I/O18
VSS
CE1
VSS
I/O13
I/O14
F VDDQ
I/O19
VSS
OE
VSS
I/O12
VDDQ
G I/O20
I/O21
BW3
NC(3)
BW2
I/O11
I/O10
H I/O22
I/O23
VSS
R/W
VSS
I/O9
I/O8
J VDDQ
VDD
VDD(2)
VDD
VSS(1)
VDD
VDDQ
K I/O24
I/O26
VSS
CLK
VSS
I/O6
I/O7
L I/O25
I/O27
BW4
NC
BW1
I/O4
I/O5
M VDDQ
I/O28
VSS
CEN
VSS
I/O3
VDDQ
N I/O29
I/O30
VSS
A1
VSS
I/O2
I/O1
P I/O31
I/OP4
VSS
A0
VSS
I/OP1
I/O0
R NC
A5
LBO
VDD
VSS(1)
A13
NC
T NC
NC
A10
A11
A14
NC
NC/ZZ(6)
,
U VDDQ NC/TMS(4) NC/TDI(4) NC/TCK(4) NC/TDO(4) NC/TRST(4,5) VDDQ
Top View
5282 drw 13A
Pin Configuration - 256K x 18, 119 BGA
1
A VDDQ
B NC
C NC
2
A6
CE2
A7
3
4
5
A4
NC(3)
A8
A3
ADV/LD
A9
A2
VDD
A13
6
7
A16
VDDQ
CE2
NC
A17
NC
D I/O8
E NC
F VDDQ
G NC
H I/O11
J VDDQ
K NC
L I/O13
M VDDQ
N I/O15
NC
I/O9
NC
I/O10
NC
VDD
I/O12
NC
I/O14
NC
VSS
VSS
VSS
BW2
VSS
VDD(2)
VSS
VSS
VSS
VSS
NC
CE1
OE
NC(3)
R/W
VDD
CLK
NC
CEN
A1
VSS
VSS
VSS
VSS
VSS
VSS(1)
VSS
BW1
VSS
VSS
I/OP1
NC
I/O6
NC
I/O4
VDD
NC
I/O2
NC
I/O1
NC
I/O7
VDDQ
I/O5
NC
VDDQ
I/O3
NC
VDDQ
NC
P NC
I/OP2
VSS
A0
VSS
NC
I/O0
R NC
A5
LBO
VDD
VSS(1)
A12
NC
T NC
A10
A15
NC
A14
A11
, NC/ZZ(6)
U VDDQ NC/TMS(4) NC/TDI(4) NC/TCK(4) NC/TDO(4) NC/TRST(4,5) VDDQ
5282 drw 13B
Top View
NOTES:
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. J3 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.
3. G4 and A4 are reserved for future 8M and 16M respectively.
4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.
6. Pin T7 supports ZZ (sleep mode) for the latest die revisions.
6.472
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