IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURES
Symbol
Parameter
IDT72V3611L15
Min.
Max.
Unit
fS
tCLK
tCLKH
tCLKL
tDS
tENS1
tENS2
tENS3
tPGS
tRSTS
tFSS
tDH
tENH1
tENH2
tENH3
tPGH
tRSTH
tFSH
tSKEW1(3)
tSKEW2(3,4)
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA or CLKB LOW
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
CSA, W/RA, before CLKA↑; CSB, W/RB before CLKB↑
ENA before CLKA↑; ENB before CLKB↑
MBA before CLKA↑; ENB before CLKB↑
Setup Time, ODD/EVEN and PGB before CLKB↑(1)
Setup Time, RST LOW before CLKA↑ or CLKB↑(2)
Setup Time, FS0 and FS1 before RST HIGH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
CSA, W/RA after CLKA↑; CSB, W/RB after CLKB↑
ENA after CLKA↑; ENB after CLKB↑
MBA after CLKA↑; MBB after CLKB↑
Hold Time, ODD/EVEN and PGB after CLKB↑(1)
Hold Time, RST LOW after CLKA↑ or CLKB↑(2)
Hold Time, FS0 and FS1 after RST HIGH
Skew Time, between CLKA↑ and CLKB↑ for EF, FF
Skew Time, between CLKA↑ and CLKB↑ for AE, AF
–
66.7
Mhz
15
–
Mhz
6
–
ns
6
–
ns
4
–
ns
6
–
ns
4
–
ns
4
–
ns
4
–
ns
5
–
ns
5
–
ns
1
–
ns
1
–
ns
1
ns
1
ns
0
–
ns
6
–
ns
4
–
ns
8
–
ns
14
–
ns
NOTES:
1. Only applies for a rising edge of CLKB that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
7