IDT72V71660DR 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72V71660DR
Integrated Device Technology
IDT72V71660DR Datasheet PDF : 31 Pages
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IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURE RANGE
TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS
Reset Value:
0000H.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
Bit Name
Description
15-13 Unused
Must be zero for normal operation
12 CFE (Complete
When Complete Frame Evaluation = 1, the Frame Evaluation is completed and bits FD11 to FD0 bits contains a valid frame alignment offset.
FrameEvaluation) This bit is reset to zero, when Start Frame Evaluation bit in the Control Register is changed from 1 to 0.
11 FD11
The falling edge of Frame Evaluation (or rising edge for GCI mode) is sampled during the CLK-HIGH phase (FD11 = 1) or during the CLK-
(Frame Delay Bit 11) LOW phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle. This bit is reset to zero when the Start Frame Evaluation
bit of the Control Register changes from 1 to 0.
10-0 FD10-0
The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the Start Frame Evaluation
(Frame Delay Bits) bit of the Control Register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
ST-BUS
Frame
CLK
Offset
Value
FE
Input
GCI
Frame
CLK
Offset
Value
FE
Input
0123
456
78
91
0
11
12
1 11 1
3 45 6
(FD[10:0] = 06H)
(FD11 = 0, sample at CLK LOW
phase)
0 1 2 3 4 5 6 7 8 91 1 1 1 1 1
0 12 3 4 5
(FD[10:0] = 09H)
(FD11 = 1, sample at CLK HIGH
phase)
5905
drw04
Figure 1. Example for Frame Alignment Measurement
10
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