IDT74ALVCH16270 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT74ALVCH16270
Integrated Device Technology
IDT74ALVCH16270 Datasheet PDF : 7 Pages
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IDT74ALVCH16270
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
PIN CONFIGURATION
OEA
1
CLKEN1B
2
2B3
3
GND
4
2B2
5
2B1
6
VCC
7
A1
8
A2
9
A3
10
GND
11
A4
12
A5
13
A6
14
A7
15
A8
16
A9
17
GND
18
A10
19
A11
20
A12
21
VCC
22
1B1
23
1B2
24
GND
25
1B3
26
CLKEN2B
27
SEL
28
56
OEB
55
CLKENA2
54
2B4
53 GND
52
2B5
51
2B6
50
VCC
49
2B7
48
2B8
47
2B9
46 GND
45
2B10
44
2B11
43
2B12
42
1B12
41
1B11
40
1B10
39 GND
38
1B9
37
1B8
36
1B7
35
VCC
34
1B6
33
1B5
32
GND
31
1B4
30
CLKENA1
29
CLK
SSOP/ TSSOP/ TVSOP
TOP VIEW
CLKENA1
L
L
L
L
H
H
H
A-TO-B STORAGE (OEB = L AND OEA = H)
Inputs
Outputs
CLKENA2 CLK
Ax
1Bx
2Bx
H
↑
L
1B0(2)
2B0(2)
H
↑
H
1B0(2)
2B0(2)
L
↑
L
L(3)
L
L
↑
H
H(3)
H
L
↑
L
1B0(4)
L
L
↑
H
1B0(4)
H
H
X or ↑
X
1B0(2)
2B0(2)
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6
V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
±50
mA
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
Continuous Current through each
ISS
VCC or GND
±100
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance VOUT = 0V
7
9
pF
CI/O
I/O Port Capacitance VIN = 0V
7
9
pF
NOTE:
1. As applicable to the device type.
FUNCTION TABLES(1)
OUTPUT ENABLE
Inputs
CLK
OEA
OEB
↑
H
H
↑
H
L
↑
L
H
↑
L
L
Outputs
Ax
1Bx, 2Bx
Z
Z
Z
Active
Active
Z
Active
Active
CLKENB1
H
X
L
L
X
X
B-TO-A STORAGE (OEA = L AND OEB = H)
Inputs
CLKENB2 CLK
SEL 1Bx 2Bx
X
X
H
X
X
H
X
L
X
X
X
↑
H
L
X
X
↑
H
H
X
L
↑
L
X
L
L
↑
L
X
H
Outputs
Ax
A (2)
0
A (2)
0
L
H
L
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
3. Two CLK edges are needed to propagate data.
4. Data present at the output of the first register.
2
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