INF85116 데이터 시트보기 (PDF) - Integral Corp.
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INF85116 Datasheet PDF : 4 Pages
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INF85116
Таble 4. I2C-bus characteristics
Symbol
Parameter
Condi-
Standard
Fast mode Unit
tions
mode
min max min max
fSCL
Clock frequency
tBUF
Time the bus must be free before
0
100
0 400 kHz
-
4.7
-
1.3
-
µs
tHD, STA
START condition hold time after which
-
first clock pulse is generated
4.0
-
0.6
-
µs
tLOW
LOW level clock period
-
4.7
-
1.3
-
µs
tHIGH
HIGH level clock period
-
4.0
-
0.6
-
µs
tSU, STA
Set-up time for START condition
repeated 4.7
-
0.6
-
µs
start
tHD, DAT
tHD, DAT
tSU, DAT
tR
Data hold time for CBUS compatible
masters
Data hold time for I2C - bus devices
Data set-up time
SDA and SCL rise time
-
note 1
-
-
5
-
-
-
µs
0
-
0
-
ns
250
-
100
-
ns
-
1000 20+0. 300 ns
1 Cb(2)
tF
tSU, STO
SDA and SCL fall time
Set-up time for STOP condition
-
-
300 20+0. 300 ns
1 Cb(2)
-
4.0
-
0.6
-
µs
Notes:
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of
SCL must be internally provided by a transmitter.
2. Cb = total capacitance of one bus line in pF.
4
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