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NM25C041

4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI™) Synchronous Bus)

Fairchild Semiconductor 

Functional Description

TABLE 1. Op Codes Table

Instruction Instruction

Name Opcode

Operation

WREN

0000 0110 Set Write Enable Latch

WRDI

0000 0100 Reset Write Enable Latch

RDSR

0000 0101 Read Status Register

WRSR

0000 0001 Write Status Register

READ

0000 A011

Read Data from Memory

Array

WRITE

0000 A010

Write Data to Memory

Array

Note: As the NM25C040 requires 9 address bits (4,096 ÷ 8 = 512 bytes = 29), the

9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I3. This

convention only applies to 4K SPI protocol.

The NM25C041 SPI device uses a CS functionality, so the device

is selected when CS is LOW (CS is to be held HIGH during

'standby' periods and between instruction sets). As stated above,

the SPI protocol defines this as a MODE 1 part, with a CLOCK

PHASE 1 and CLOCK POLARITY 0. This means that the part is

active with CS = 0 (VIL), all INPUT data is latched into the device

on the RISING edge of SCK and all OUTPUT data is clocked out

on the FALLING edge of SCK.

,,,,FIGURE 3. SPI Protocol

CS

SCK

…

SI

Bit 7 Bit 6

…

SO

Bit 7 Bit 6

…

,,,,Bit1 Bit0

Bit 1 Bit 0

DS800002-5

The HOLD pin operation is used when the device is selected (CS

LOW) and the application requires that the SI datastream be

stopped and then restarted. The HOLD pin allows a fully 'static'

operation, wherin the device may be put on HOLD by bringing the

HOLD pin LOW (VIL). During the HOLD state, SCK must be HIGH

and CS must remain LOW (device selected). In order to resume

EEPROM serial communication, HOLD must be again brought

HIGH and the SCK/SI signals resumed. During the HOLD state,

SO is tri-stated (high impedance).

As an additional protection against data corruption, the device is

designed so that, if an invalid opcode is received, the device will

not shift any further data into the SI latches and SO will remain tri-

stated. In this case, CS must again be brought HIGH to re-initialize

the device and a new opcode re-entered. See Figure 4.

,,,,, FIGURE 4. Invalid Op-Code

CS

SI

INVALID OP-CODE

SO

DS800002-7

READ STATUS REGISTER (RDSR): The Read Status Register

(RDSR) instruction provides access to the status register which is

used to interrogate the READY/BUSY and WRITE ENABLE

status of the chip. Two non-volatile status register bits are used to

select one of four levels of BLOCK WRITE PROTECTION. The

status register format is shown in Table 2.

READ SEQUENCE: Reading the memory via the SPI link re-

quires the following sequence. The CS line is pulled low to select

the device. The READ op-code (which includes A8) is transmitted

on the SI line followed by the byte address (A7–A0) to be read.

After this is done, data on the SI line becomes don’t care. The data

(D7–D0) at the address specified is then shifted out on the SO line.

If only one byte is to be read, the CS line can be pulled back to the

high level. It is possible to continue the READ sequence as the

byte address is automatically incremented and data will continue

to be shifted out. When the highest address is reached (1FF), the

address counter rolls over to lowest address (000) allowing the

entire memory to be read in one continuous READ cycle. See

Figure 5.

FIGURE 5. Read Sequence

,,,,,, CS

SI

READ

OP-CODE

BYTE

ADDR (n)

SO

DATA

(n)

DATA

(n+1)

DATA

(n+2)

DATA

(n+3)

DS800002-8

NM25C041 Rev. D.1

6

www.fairchildsemi.com

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