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NM25C041

4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI™) Synchronous Bus)

Fairchild Semiconductor 

Functional Description (Continued)

TABLE 2. Status Register Format

Bit Bit Bit Bit Bit Bit Bit Bit

7 65 43 210

WRITE DISABLE (WRDI): To protect against accidental data

disturbance the WRITE DISABLE (WRDI) instruction disables all

programming modes. The WRITE DISABLE instruction is inde-

pendent of the status of the WP pin. See Figure 8.

X

X

X

X BP1 BP0 WEN RDY

X = Don't Care

Status register Bit 0 = 0 (RDY) indicates that the device is READY;

Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0

(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =

1 indicates that the device is WRITE ENABLED. Non-volatile

status register Bits 2 and 3 (BP0 and BP1) indicate the level of

BLOCK WRITE PROTECTION selected. The block write protec-

,,,,, FIGURE 8. Write Disable

CS

SI

WRDI OP-CODE

SO

DS800002-11

tion levels and corresponding status register control bits are WRITE SEQUENCE: To program the device the WRITE PRO-

shown in Table 3. Note that if a RDSR instruction is executed TECT (WP) pin must be held high and two separate instructions

during a programming cycle only the RDY bit is valid. All must be executed. The chip must first be write enabled via the

other bits are 1s. See Figure 6.

WRITE ENABLE instruction and then a WRITE instruction must

TABLE 3. Block Write Protection Levels

be executed. Moreover, the address of the memory location(s) to

be programmed must be outside the protected address field

Level Status Register Bits Array

selected by the Block Write Protection Level. See Table 3.

Address

A WRITE command requires the following sequence. The CS line

BP1

BP0

Protected

is pulled low to select the device, then the WRITE op-code (which

includes A8) is transmitted on the SI line followed by the byte

0

0

0

None

address (A7–A0) and the corresponding pro-data (D7–D0) to be

1

0

1

180–1FF

programmed. Programming will start after the CS pin is forced

back to a high level. Note that the LOW to HIGH transition of the

2

1

0

100–1FF

CS pin must occur during the SCK low time immediately after

3

1

1

000–1FF

clocking in the D0 data bit. The READY/BUSY status of the device

can be determined by executing a READ STATUS REGISTER

FIGURE 6. Read Status

CS

SI

RDSR

OP-CODE

SO

SR_DATA

MSB...LSB

,
,
,
,
,DS800002-9

,,,,,, WRITE ENABLE (WREN): When VCC is applied to the chip, it

“powers up” in the write disable state. Therefore, all modes must

be preceded by a WRITE ENABLE (WREN) instruction. Addition-

,,,,,, ally the WP pin must be held high during a WRITE ENABLE

(RDSR) instruction. Bit 0 = 1 indicates that the WRITE cycle is still

in progress and Bit 0 = 0 indicates that the WRITE cycle has

ended. During the WRITE programming cycle (Bit 0 = 1) only the

READ STATUS REGISTER instruction is enabled.

FIGURE 9. Start WRITE Condition

CS

SCK

SI

D2

D1

D0

SO

DS800002-12

instruction. At the completion of a WRITE or WRSR cycle the

device is automatically turned to the write disable state. Note that

a WRITE DISABLE (WRDI) instruction or forcing the WP pin low

will also return the device to the write disable state. See Figure 7.

,,,,, FIGURE 7. Write Enable

CS

SI

WREN OP-CODE

SO

DS800002-10

NM25C041 Rev. D.1

7

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